454 lines
14 KiB
Coq
454 lines
14 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This is the LVDS/DDR interface, note that overrange is independent of data path,
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// software will not be able to relate overrange to a specific sample!
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// Alternative is to concatenate sample value and or status for data.
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`timescale 1ns/100ps
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module axi_ad9643_if (
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// adc interface (clk, data, over-range)
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adc_clk_in_p,
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adc_clk_in_n,
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adc_data_in_p,
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adc_data_in_n,
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adc_or_in_p,
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adc_or_in_n,
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// interface outputs
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adc_clk,
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adc_data_a,
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adc_data_b,
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adc_or_a,
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adc_or_b,
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adc_status,
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// processor control signals
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adc_ddr_edgesel,
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adc_pin_mode,
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// delay control signals
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delay_clk,
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delay_rst,
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delay_sel,
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delay_rwn,
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delay_addr,
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delay_wdata,
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delay_rdata,
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delay_ack_t,
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delay_locked);
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// This parameter controls the buffer type based on the target device.
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parameter PCORE_DEVICE_TYPE = 0;
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parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
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localparam PCORE_DEVICE_7SERIES = 0;
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localparam PCORE_DEVICE_VIRTEX6 = 1;
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// adc interface (clk, data, over-range)
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input adc_clk_in_p;
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input adc_clk_in_n;
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input [13:0] adc_data_in_p;
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input [13:0] adc_data_in_n;
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input adc_or_in_p;
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input adc_or_in_n;
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// interface outputs
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output adc_clk;
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output [13:0] adc_data_a;
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output [13:0] adc_data_b;
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output adc_or_a;
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output adc_or_b;
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output adc_status;
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// processor control signals
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input adc_ddr_edgesel;
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input adc_pin_mode;
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// delay control signals
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input delay_clk;
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input delay_rst;
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input delay_sel;
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input delay_rwn;
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input [ 7:0] delay_addr;
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input [ 4:0] delay_wdata;
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output [ 4:0] delay_rdata;
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output delay_ack_t;
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output delay_locked;
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// internal registers
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reg adc_status = 'd0;
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reg [13:0] adc_data_p = 'd0;
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reg [13:0] adc_data_n = 'd0;
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reg [13:0] adc_data_n_d = 'd0;
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reg adc_or_p = 'd0;
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reg adc_or_n = 'd0;
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reg adc_or_n_d = 'd0;
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reg [13:0] adc_data_mux_a = 'd0;
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reg [13:0] adc_data_mux_b = 'd0;
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reg adc_or_mux_a = 'd0;
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reg adc_or_mux_b = 'd0;
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reg [13:0] adc_data_a = 'd0;
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reg [13:0] adc_data_b = 'd0;
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reg adc_or_a = 'd0;
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reg adc_or_b = 'd0;
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reg [14:0] delay_ld = 'd0;
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reg delay_ack_t = 'd0;
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reg [ 4:0] delay_rdata = 'd0;
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// internal signals
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wire [ 4:0] delay_rdata_s[14:0];
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wire [13:0] adc_data_ibuf_s;
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wire [13:0] adc_data_idelay_s;
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wire [13:0] adc_data_p_s;
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wire [13:0] adc_data_n_s;
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wire adc_or_ibuf_s;
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wire adc_or_idelay_s;
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wire adc_or_p_s;
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wire adc_or_n_s;
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wire adc_clk_ibuf_s;
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// instantiation variables
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genvar l_inst;
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// The adc data is 14bits ddr, and here it is demuxed to 16bits.
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// The samples may be selected to be either positive first, or negative first.
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// Two data pin modes are supported- data can either be clock edge muxed (rising or falling edges),
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// or within a clock edge, pin muxed (lower 7 bits and upper 7 bits)
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always @(posedge adc_clk) begin
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adc_status <= 1'b1;
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adc_data_p <= adc_data_p_s;
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adc_data_n <= adc_data_n_s;
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adc_data_n_d <= adc_data_n;
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adc_or_p <= adc_or_p_s;
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adc_or_n <= adc_or_n_s;
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adc_or_n_d <= adc_or_n;
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if (adc_ddr_edgesel == 1'b1) begin
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adc_data_mux_a <= adc_data_p;
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adc_data_mux_b <= adc_data_n;
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adc_or_mux_a <= adc_or_p;
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adc_or_mux_b <= adc_or_n;
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end else begin
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adc_data_mux_a <= adc_data_n_d;
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adc_data_mux_b <= adc_data_p;
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adc_or_mux_a <= adc_or_n_d;
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adc_or_mux_b <= adc_or_p;
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end
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if (adc_pin_mode == 1'b1) begin
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adc_data_a <= adc_data_mux_a;
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adc_data_b <= adc_data_mux_b;
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adc_or_a <= adc_or_mux_a;
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adc_or_b <= adc_or_mux_b;
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end else begin
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adc_data_a <= { adc_data_mux_b[13], adc_data_mux_a[13],
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adc_data_mux_b[12], adc_data_mux_a[12],
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adc_data_mux_b[11], adc_data_mux_a[11],
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adc_data_mux_b[10], adc_data_mux_a[10],
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adc_data_mux_b[ 9], adc_data_mux_a[ 9],
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adc_data_mux_b[ 8], adc_data_mux_a[ 8],
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adc_data_mux_b[ 7], adc_data_mux_a[ 7]};
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adc_data_b <= { adc_data_mux_b[ 6], adc_data_mux_a[ 6],
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adc_data_mux_b[ 5], adc_data_mux_a[ 5],
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adc_data_mux_b[ 4], adc_data_mux_a[ 4],
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adc_data_mux_b[ 3], adc_data_mux_a[ 3],
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adc_data_mux_b[ 2], adc_data_mux_a[ 2],
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adc_data_mux_b[ 1], adc_data_mux_a[ 1],
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adc_data_mux_b[ 0], adc_data_mux_a[ 0]};
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adc_or_a <= adc_or_mux_a;
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adc_or_b <= adc_or_mux_b;
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end
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end
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// The delay control interface, each delay element can be individually
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// addressed, and a delay value can be directly loaded (no INC/DEC stuff)
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always @(posedge delay_clk) begin
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if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
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case (delay_addr)
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8'h0e: delay_ld <= 15'h4000;
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8'h0d: delay_ld <= 15'h2000;
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8'h0c: delay_ld <= 15'h1000;
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8'h0b: delay_ld <= 15'h0800;
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8'h0a: delay_ld <= 15'h0400;
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8'h09: delay_ld <= 15'h0200;
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8'h08: delay_ld <= 15'h0100;
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8'h07: delay_ld <= 15'h0080;
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8'h06: delay_ld <= 15'h0040;
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8'h05: delay_ld <= 15'h0020;
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8'h04: delay_ld <= 15'h0010;
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8'h03: delay_ld <= 15'h0008;
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8'h02: delay_ld <= 15'h0004;
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8'h01: delay_ld <= 15'h0002;
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8'h00: delay_ld <= 15'h0001;
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default: delay_ld <= 15'h0000;
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endcase
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end else begin
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delay_ld <= 15'h0000;
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end
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if (delay_sel == 1'b1) begin
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delay_ack_t <= ~delay_ack_t;
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end
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case (delay_addr)
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8'h0e: delay_rdata <= delay_rdata_s[14];
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8'h0d: delay_rdata <= delay_rdata_s[13];
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8'h0c: delay_rdata <= delay_rdata_s[12];
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8'h0b: delay_rdata <= delay_rdata_s[11];
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8'h0a: delay_rdata <= delay_rdata_s[10];
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8'h09: delay_rdata <= delay_rdata_s[ 9];
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8'h08: delay_rdata <= delay_rdata_s[ 8];
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8'h07: delay_rdata <= delay_rdata_s[ 7];
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8'h06: delay_rdata <= delay_rdata_s[ 6];
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8'h05: delay_rdata <= delay_rdata_s[ 5];
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8'h04: delay_rdata <= delay_rdata_s[ 4];
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8'h03: delay_rdata <= delay_rdata_s[ 3];
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8'h02: delay_rdata <= delay_rdata_s[ 2];
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8'h01: delay_rdata <= delay_rdata_s[ 1];
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8'h00: delay_rdata <= delay_rdata_s[ 0];
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default: delay_rdata <= 5'd0;
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endcase
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end
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// The data interface, data signals goes through a LVDS input buffer, then
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// a delay element (1/32th of a 200MHz clock) and finally an input DDR demux.
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generate
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for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
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IBUFDS i_data_ibuf (
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.I (adc_data_in_p[l_inst]),
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.IB (adc_data_in_n[l_inst]),
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.O (adc_data_ibuf_s[l_inst]));
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if (PCORE_DEVICE_TYPE == PCORE_DEVICE_VIRTEX6) begin
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(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
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IODELAYE1 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("I"),
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.HIGH_PERFORMANCE_MODE ("TRUE"),
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.IDELAY_TYPE ("VAR_LOADABLE"),
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.IDELAY_VALUE (0),
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.ODELAY_TYPE ("FIXED"),
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.ODELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.SIGNAL_PATTERN ("DATA"))
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i_data_idelay (
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.T (1'b1),
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.CE (1'b0),
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.INC (1'b0),
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.CLKIN (1'b0),
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.DATAIN (1'b0),
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.ODATAIN (1'b0),
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.CINVCTRL (1'b0),
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.C (delay_clk),
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.IDATAIN (adc_data_ibuf_s[l_inst]),
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.DATAOUT (adc_data_idelay_s[l_inst]),
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.RST (delay_ld[l_inst]),
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.CNTVALUEIN (delay_wdata),
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.CNTVALUEOUT (delay_rdata_s[l_inst]));
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end else begin
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(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
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IDELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("IDATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.IDELAY_TYPE ("VAR_LOAD"),
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.IDELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.PIPE_SEL ("FALSE"),
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.SIGNAL_PATTERN ("DATA"))
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i_data_idelay (
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.CE (1'b0),
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.INC (1'b0),
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.DATAIN (1'b0),
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.LDPIPEEN (1'b0),
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.CINVCTRL (1'b0),
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.REGRST (1'b0),
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.C (delay_clk),
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.IDATAIN (adc_data_ibuf_s[l_inst]),
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.DATAOUT (adc_data_idelay_s[l_inst]),
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.LD (delay_ld[l_inst]),
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.CNTVALUEIN (delay_wdata),
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.CNTVALUEOUT (delay_rdata_s[l_inst]));
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end
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IDDR #(
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.INIT_Q1 (1'b0),
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.INIT_Q2 (1'b0),
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.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
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.SRTYPE ("ASYNC"))
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i_data_ddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (adc_clk),
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||
|
|
.D (adc_data_idelay_s[l_inst]),
|
||
|
|
.Q1 (adc_data_p_s[l_inst]),
|
||
|
|
.Q2 (adc_data_n_s[l_inst]));
|
||
|
|
|
||
|
|
end
|
||
|
|
endgenerate
|
||
|
|
|
||
|
|
// The over-range interface, it follows a similar path as the data signals.
|
||
|
|
|
||
|
|
IBUFDS i_or_ibuf (
|
||
|
|
.I (adc_or_in_p),
|
||
|
|
.IB (adc_or_in_n),
|
||
|
|
.O (adc_or_ibuf_s));
|
||
|
|
|
||
|
|
generate
|
||
|
|
if (PCORE_DEVICE_TYPE == PCORE_DEVICE_VIRTEX6) begin
|
||
|
|
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
|
||
|
|
IODELAYE1 #(
|
||
|
|
.CINVCTRL_SEL ("FALSE"),
|
||
|
|
.DELAY_SRC ("I"),
|
||
|
|
.HIGH_PERFORMANCE_MODE ("TRUE"),
|
||
|
|
.IDELAY_TYPE ("VAR_LOADABLE"),
|
||
|
|
.IDELAY_VALUE (0),
|
||
|
|
.ODELAY_TYPE ("FIXED"),
|
||
|
|
.ODELAY_VALUE (0),
|
||
|
|
.REFCLK_FREQUENCY (200.0),
|
||
|
|
.SIGNAL_PATTERN ("DATA"))
|
||
|
|
i_or_idelay (
|
||
|
|
.T (1'b1),
|
||
|
|
.CE (1'b0),
|
||
|
|
.INC (1'b0),
|
||
|
|
.CLKIN (1'b0),
|
||
|
|
.DATAIN (1'b0),
|
||
|
|
.ODATAIN (1'b0),
|
||
|
|
.CINVCTRL (1'b0),
|
||
|
|
.C (delay_clk),
|
||
|
|
.IDATAIN (adc_or_ibuf_s),
|
||
|
|
.DATAOUT (adc_or_idelay_s),
|
||
|
|
.RST (delay_ld[14]),
|
||
|
|
.CNTVALUEIN (delay_wdata),
|
||
|
|
.CNTVALUEOUT (delay_rdata_s[14]));
|
||
|
|
end else begin
|
||
|
|
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
|
||
|
|
IDELAYE2 #(
|
||
|
|
.CINVCTRL_SEL ("FALSE"),
|
||
|
|
.DELAY_SRC ("IDATAIN"),
|
||
|
|
.HIGH_PERFORMANCE_MODE ("FALSE"),
|
||
|
|
.IDELAY_TYPE ("VAR_LOAD"),
|
||
|
|
.IDELAY_VALUE (0),
|
||
|
|
.REFCLK_FREQUENCY (200.0),
|
||
|
|
.PIPE_SEL ("FALSE"),
|
||
|
|
.SIGNAL_PATTERN ("DATA"))
|
||
|
|
i_or_idelay (
|
||
|
|
.CE (1'b0),
|
||
|
|
.INC (1'b0),
|
||
|
|
.DATAIN (1'b0),
|
||
|
|
.LDPIPEEN (1'b0),
|
||
|
|
.CINVCTRL (1'b0),
|
||
|
|
.REGRST (1'b0),
|
||
|
|
.C (delay_clk),
|
||
|
|
.IDATAIN (adc_or_ibuf_s),
|
||
|
|
.DATAOUT (adc_or_idelay_s),
|
||
|
|
.LD (delay_ld[14]),
|
||
|
|
.CNTVALUEIN (delay_wdata),
|
||
|
|
.CNTVALUEOUT (delay_rdata_s[14]));
|
||
|
|
end
|
||
|
|
endgenerate
|
||
|
|
|
||
|
|
IDDR #(
|
||
|
|
.INIT_Q1 (1'b0),
|
||
|
|
.INIT_Q2 (1'b0),
|
||
|
|
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
|
||
|
|
.SRTYPE ("ASYNC"))
|
||
|
|
i_or_ddr (
|
||
|
|
.CE (1'b1),
|
||
|
|
.R (1'b0),
|
||
|
|
.S (1'b0),
|
||
|
|
.C (adc_clk),
|
||
|
|
.D (adc_or_idelay_s),
|
||
|
|
.Q1 (adc_or_p_s),
|
||
|
|
.Q2 (adc_or_n_s));
|
||
|
|
|
||
|
|
// The clock path is a simple clock buffer after a LVDS input buffer.
|
||
|
|
// It is possible for this logic to be replaced with a OSERDES based data capture.
|
||
|
|
// The reason for such a simple interface here is because this reference design
|
||
|
|
// is used for various boards (native fmc and/or evaluation boards). The pinouts
|
||
|
|
// of the FPGA - ADC interface is probably do not allow a OSERDES placement.
|
||
|
|
|
||
|
|
IBUFGDS i_clk_ibuf (
|
||
|
|
.I (adc_clk_in_p),
|
||
|
|
.IB (adc_clk_in_n),
|
||
|
|
.O (adc_clk_ibuf_s));
|
||
|
|
|
||
|
|
generate
|
||
|
|
if (PCORE_DEVICE_TYPE == PCORE_DEVICE_VIRTEX6) begin
|
||
|
|
BUFR #(.BUFR_DIVIDE ("BYPASS")) i_clk_gbuf (
|
||
|
|
.CLR (1'b0),
|
||
|
|
.CE (1'b1),
|
||
|
|
.I (adc_clk_ibuf_s),
|
||
|
|
.O (adc_clk));
|
||
|
|
end else begin
|
||
|
|
BUFG i_clk_gbuf (
|
||
|
|
.I (adc_clk_ibuf_s),
|
||
|
|
.O (adc_clk));
|
||
|
|
end
|
||
|
|
endgenerate
|
||
|
|
|
||
|
|
// The delay controller. Refer to Xilinx doc. for details.
|
||
|
|
// The GROUP directive controls which delay elements this is associated with.
|
||
|
|
|
||
|
|
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
|
||
|
|
IDELAYCTRL i_delay_ctrl (
|
||
|
|
.RST (delay_rst),
|
||
|
|
.REFCLK (delay_clk),
|
||
|
|
.RDY (delay_locked));
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
// ***************************************************************************
|
||
|
|
// ***************************************************************************
|
||
|
|
|