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pluto_hdl_adi/projects/fmcadc2/vc707/system_project.tcl

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renamed to match official names
2014-12-08 15:44:15 +00:00
source ../../scripts/adi_env.tcl
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2018-08-14 08:43:32 +00:00
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
fmcadc2/vc707: 2014.4 updates
2015-03-26 19:07:15 +00:00
source $ad_hdl_dir/projects/scripts/adi_board.tcl
renamed to match official names
2014-12-08 15:44:15 +00:00
fmcadc2: Parameterize JESD204 configuration values Add the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-07 16:33:27 +00:00
# get_env_param retrieves parameter value from the environment if exists,
# other case use the default value
#
# Use over-writable parameters from the environment.
#
# e.g.
# make RX_JESD_L=8
# Parameter description:
# RX_JESD_M : Number of converters per link
# RX_JESD_L : Number of lanes per link
# RX_JESD_S : Number of samples per frame
# RX_JESD_NP : Number of bits per sample
adi_project fmcadc2_vc707 0 [list \
RX_JESD_M [get_env_param RX_JESD_M 1 ] \
RX_JESD_L [get_env_param RX_JESD_L 8 ] \
RX_JESD_S [get_env_param RX_JESD_S 4 ] \
RX_JESD_NP [get_env_param RX_JESD_NP 16] \
]
renamed to match official names
2014-12-08 15:44:15 +00:00
adi_project_files fmcadc2_vc707 [list \
"../common/fmcadc2_spi.v" \
"system_top.v" \
fmcadc2/vc707: 2014.4 updates
2015-03-26 19:07:15 +00:00
"system_constr.xdc" \
library: Move ad_iobuf to the common library, as it's not Xilinx specific Updated all system_project and Makefiles
2020-09-23 08:30:18 +00:00
"$ad_hdl_dir/library/common/ad_iobuf.v" \
fmcadc2: Integrate ad_sysref_gen into the project
2016-12-19 12:16:05 +00:00
"$ad_hdl_dir/library/common/ad_sysref_gen.v" \
renamed to match official names
2014-12-08 15:44:15 +00:00
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
fmcadc2/vc707: Disabele axi_spi constraint file The interface ports of the AXI SPI IP are not connected directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 17:15:44 +00:00
set_property is_enabled false [get_files *system_axi*_spi*.xdc]
renamed to match official names
2014-12-08 15:44:15 +00:00
adi_project_run fmcadc2_vc707