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pluto_hdl_adi/projects/usdrx1/zc706/system_bd.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
projects/system_bd- adc/dac fifo board designs
2017-02-27 21:05:21 +00:00
set adc_fifo_name usdrx1_fifo
set adc_fifo_address_width 18
set adc_data_width 512
set adc_dma_data_width 64
axi_adc/dacfifo: Split the intergration script file Split the integration script file into two separate script files. Rename the integration processes names to be more meaningful.
2016-05-05 06:40:25 +00:00
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
file renamed; sed output; fingers crossed
2017-02-22 20:56:37 +00:00
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
usdrx1: Add DDR FIFO The converters on the usdrx1 generate 2.5GB/s. This more than we can transport over the HP interconnects to the system memory. Add a dedicated DDR FIFO to design which can be used to buffer the data before it is transferred to the main memory. Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA FIFO size from 4 to 8, so we can transfer the captured data faster to the main memory. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 08:42:06 +00:00
source ../common/usdrx1_bd.tcl
projects/system_bd- adc/dac fifo board designs
2017-02-27 21:05:21 +00:00