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pluto_hdl_adi/library/axi_adrv9009/axi_adrv9009_ip.tcl

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axi_ad9379: Initial commit
2017-09-01 14:26:37 +00:00
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
adi_ip_create axi_adrv9009
adi_ip_files axi_adrv9009 [list \
axi_ad9379: Initial commit
2017-09-01 14:26:37 +00:00
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"$ad_hdl_dir/library/common/ad_rst.v" \
Move Xilinx specific DC filter implementation to library/xilinx/common/ The DC filter implementation in library/common/dc_filter.v is Xilinx specific as it uses the Xilinx DSP48 hard-macro. There is a matching Altera specific implementation in library/altera/common/dc_filter.v. Move the Xilinx specific implementation from the generic common folder to the Xilinx specific common folder in library/xilinx/common/ since that is where all other Xilinx specific common modules reside. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:31:50 +00:00
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
axi_ad9379: Initial commit
2017-09-01 14:26:37 +00:00
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
axi_ad9379: Update for CORDIC algorithm Add the new files to the IP list Propagate DDS parameters to top file
2018-02-07 12:50:46 +00:00
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
axi_ad9379: Initial commit
2017-09-01 14:26:37 +00:00
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
axi_adrv9009: Updates for ad_dds phase acc wrapper
2018-06-06 11:13:59 +00:00
"$ad_hdl_dir/library/common/ad_dds_2.v" \
axi_ad9379: Initial commit
2017-09-01 14:26:37 +00:00
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
"axi_adrv9009_if.v" \
"axi_adrv9009_rx_channel.v" \
"axi_adrv9009_rx.v" \
"axi_adrv9009_rx_os.v" \
"axi_adrv9009_tx_channel.v" \
"axi_adrv9009_tx.v" \
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
"axi_adrv9009.v" \
"bd/bd.tcl" ]
axi_ad9379: Initial commit
2017-09-01 14:26:37 +00:00
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
adi_ip_properties axi_adrv9009
axi_ad9379: Initial commit
2017-09-01 14:26:37 +00:00
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
adi_ip_bd axi_adrv9009 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
axi_ad9379: Initial commit
2017-09-01 14:26:37 +00:00
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]]
axi_*: Infer clock and reset signals of an IP A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip
2018-02-15 08:41:14 +00:00
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_os_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
axi_ad9379: Initial commit
2017-09-01 14:26:37 +00:00
ipx::save_core [ipx::current_core]