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pluto_hdl_adi/library/interfaces/Makefile

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pzsdr: Add untracked Makefiles
2015-10-16 10:58:36 +00:00
####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
Add quiet mode to the Makefile system The standard Makefile output is very noisy and it can be difficult to filter the interesting information from this noise. In quiet mode the standard Makefile output will be suppressed and instead a short human readable description of the current task is shown. E.g. > make adv7511.zed Building axi_clkgen library [library/axi_clkgen/axi_clkgen_ip.log] ... OK Building axi_hdmi_tx library [library/axi_hdmi_tx/axi_hdmi_tx_ip.log] ... OK Building axi_i2s_adi library [library/axi_i2s_adi/axi_i2s_adi_ip.log] ... OK Building axi_spdif_tx library [library/axi_spdif_tx/axi_spdif_tx_ip.log] ... OK Building util_i2c_mixer library [library/util_i2c_mixer/util_i2c_mixer_ip.log] ... OK Building adv7511_zed project [projects/adv7511/zed/adv7511_zed_vivado.log] ... OK Quiet mode is enabled by default since it generates a more human readable output. It can be disabled by passing VERBOSE=1 to make or setting the VERBOSE environment variable to 1 before calling make. E.g. > make adv7511.zed VERBOSE=1 make[1]: Entering directory 'library/axi_clkgen' rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil .timestamp_altera vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1 ... Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-25 07:21:37 +00:00
include ../../quiet.mk
Makefiles: Updated Makefiles
2015-10-23 07:44:27 +00:00
M_DEPS := interfaces_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
all: Rename altera to intel
2018-08-13 13:59:02 +00:00
M_DEPS += ../scripts/adi_ip_xilinx.tcl
pzsdr: Add untracked Makefiles
2015-10-16 10:58:36 +00:00
Makefiles: Updated Makefiles
2015-10-23 07:44:27 +00:00
M_VIVADO := vivado -mode batch -source
pzsdr: Add untracked Makefiles
2015-10-16 10:58:36 +00:00
Makefile: Update Makefiles
2016-03-14 07:31:17 +00:00
M_FLIST := *.log
Makefiles: Updated Makefiles
2015-10-23 07:44:27 +00:00
M_FLIST += *.jou
make updates
2016-07-06 19:02:00 +00:00
M_FLIST += if_xcvr_cm.xml
M_FLIST += if_xcvr_cm_rtl.xml
M_FLIST += if_xcvr_ch.xml
M_FLIST += if_xcvr_ch_rtl.xml
Makefile: Update Makefiles
2016-03-14 07:31:17 +00:00
M_FLIST += if_gt_qpll.xml
M_FLIST += if_gt_qpll_rtl.xml
M_FLIST += if_gt_pll.xml
M_FLIST += if_gt_pll_rtl.xml
M_FLIST += if_gt_rx.xml
M_FLIST += if_gt_rx_rtl.xml
M_FLIST += if_gt_tx.xml
M_FLIST += if_gt_tx_rtl.xml
M_FLIST += if_gt_rx_ksig.xml
M_FLIST += if_gt_rx_ksig_rtl.xml
Makefiles: Updated Makefiles
2015-10-23 07:44:27 +00:00
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
.PHONY: all xilinx clean clean-all
all: xilinx
xilinx: if_xcvr_cm.xml if_xcvr_cm_rtl.xml if_xcvr_ch.xml if_xcvr_ch_rtl.xml if_gt_qpll.xml if_gt_qpll_rtl.xml if_gt_pll.xml if_gt_pll_rtl.xml if_gt_rx.xml if_gt_rx_rtl.xml if_gt_tx.xml if_gt_tx_rtl.xml if_gt_rx_ksig.xml if_gt_rx_ksig_rtl.xml
Makefiles: Updated Makefiles
2015-10-23 07:44:27 +00:00
clean:clean-all
pzsdr: Add untracked Makefiles
2015-10-16 10:58:36 +00:00
clean-all:
Add quiet mode to the Makefile system The standard Makefile output is very noisy and it can be difficult to filter the interesting information from this noise. In quiet mode the standard Makefile output will be suppressed and instead a short human readable description of the current task is shown. E.g. > make adv7511.zed Building axi_clkgen library [library/axi_clkgen/axi_clkgen_ip.log] ... OK Building axi_hdmi_tx library [library/axi_hdmi_tx/axi_hdmi_tx_ip.log] ... OK Building axi_i2s_adi library [library/axi_i2s_adi/axi_i2s_adi_ip.log] ... OK Building axi_spdif_tx library [library/axi_spdif_tx/axi_spdif_tx_ip.log] ... OK Building util_i2c_mixer library [library/util_i2c_mixer/util_i2c_mixer_ip.log] ... OK Building adv7511_zed project [projects/adv7511/zed/adv7511_zed_vivado.log] ... OK Quiet mode is enabled by default since it generates a more human readable output. It can be disabled by passing VERBOSE=1 to make or setting the VERBOSE environment variable to 1 before calling make. E.g. > make adv7511.zed VERBOSE=1 make[1]: Entering directory 'library/axi_clkgen' rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil .timestamp_altera vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1 ... Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-25 07:21:37 +00:00
$(call clean, \
$(M_FLIST), \
interface definitions)
Makefiles: Updated Makefiles
2015-10-23 07:44:27 +00:00
interfaces: Add dependencies to rule Make sure that the XML files are re-build when any of the scripts that are used to generated it are modified. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 09:10:02 +00:00
%.xml: $(M_DEPS)
Add quiet mode to the Makefile system The standard Makefile output is very noisy and it can be difficult to filter the interesting information from this noise. In quiet mode the standard Makefile output will be suppressed and instead a short human readable description of the current task is shown. E.g. > make adv7511.zed Building axi_clkgen library [library/axi_clkgen/axi_clkgen_ip.log] ... OK Building axi_hdmi_tx library [library/axi_hdmi_tx/axi_hdmi_tx_ip.log] ... OK Building axi_i2s_adi library [library/axi_i2s_adi/axi_i2s_adi_ip.log] ... OK Building axi_spdif_tx library [library/axi_spdif_tx/axi_spdif_tx_ip.log] ... OK Building util_i2c_mixer library [library/util_i2c_mixer/util_i2c_mixer_ip.log] ... OK Building adv7511_zed project [projects/adv7511/zed/adv7511_zed_vivado.log] ... OK Quiet mode is enabled by default since it generates a more human readable output. It can be disabled by passing VERBOSE=1 to make or setting the VERBOSE environment variable to 1 before calling make. E.g. > make adv7511.zed VERBOSE=1 make[1]: Entering directory 'library/axi_clkgen' rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil .timestamp_altera vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1 ... Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-25 07:21:37 +00:00
$(call build, \
$(M_VIVADO) interfaces_ip.tcl, \
interfaces_ip.log, \
interface definitions)
make updates
2016-07-06 19:02:00 +00:00
pzsdr: Add untracked Makefiles
2015-10-16 10:58:36 +00:00
####################################################################################
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