2015-06-26 09:04:19 +00:00
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// ***************************************************************************
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// ***************************************************************************
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2017-05-17 08:44:52 +00:00
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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2017-04-20 15:43:37 +00:00
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//
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2017-05-29 06:55:41 +00:00
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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2017-04-20 15:43:37 +00:00
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//
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2017-05-29 06:55:41 +00:00
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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2017-04-20 15:43:37 +00:00
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//
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2017-05-17 08:44:52 +00:00
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// 1. The GNU General Public License version 2 as published by the
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2017-05-29 06:55:41 +00:00
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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2017-05-17 08:44:52 +00:00
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//
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// OR
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//
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2017-05-29 06:55:41 +00:00
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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2015-06-26 09:04:19 +00:00
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//
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// ***************************************************************************
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// ***************************************************************************
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2015-08-19 11:11:47 +00:00
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// MMCM_OR_BUFR_N with DRP and device specific
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2015-06-26 09:04:19 +00:00
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`timescale 1ns/100ps
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2017-04-13 08:45:54 +00:00
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module ad_mmcm_drp #(
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parameter MMCM_DEVICE_TYPE = 0,
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parameter MMCM_CLKIN_PERIOD = 1.667,
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parameter MMCM_CLKIN2_PERIOD = 1.667,
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parameter MMCM_VCO_DIV = 6,
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parameter MMCM_VCO_MUL = 12.000,
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parameter MMCM_CLK0_DIV = 2.000,
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parameter MMCM_CLK0_PHASE = 0.000,
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parameter MMCM_CLK1_DIV = 6,
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parameter MMCM_CLK1_PHASE = 0.000,
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parameter MMCM_CLK2_DIV = 2.000,
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parameter MMCM_CLK2_PHASE = 0.000) (
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2015-06-26 09:04:19 +00:00
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// clocks
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2017-04-13 08:45:54 +00:00
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input clk,
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input clk2,
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input clk_sel,
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input mmcm_rst,
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output mmcm_clk_0,
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output mmcm_clk_1,
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output mmcm_clk_2,
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2015-06-26 09:04:19 +00:00
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// drp interface
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2017-04-13 08:45:54 +00:00
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input up_clk,
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input up_rstn,
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input up_drp_sel,
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input up_drp_wr,
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input [11:0] up_drp_addr,
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input [15:0] up_drp_wdata,
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output reg [15:0] up_drp_rdata,
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output reg up_drp_ready,
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output reg up_drp_locked);
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2015-06-26 09:04:19 +00:00
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localparam MMCM_DEVICE_7SERIES = 0;
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localparam MMCM_DEVICE_VIRTEX6 = 1;
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// internal registers
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reg up_drp_locked_m1 = 'd0;
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// internal signals
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wire bufg_fb_clk_s;
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wire mmcm_fb_clk_s;
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wire mmcm_clk_0_s;
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wire mmcm_clk_1_s;
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2016-03-22 16:49:30 +00:00
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wire mmcm_clk_2_s;
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2015-06-26 09:04:19 +00:00
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wire mmcm_locked_s;
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wire [15:0] up_drp_rdata_s;
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wire up_drp_ready_s;
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// drp read and locked
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_drp_rdata <= 'd0;
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up_drp_ready <= 'd0;
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up_drp_locked_m1 <= 1'd0;
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up_drp_locked <= 1'd0;
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end else begin
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up_drp_rdata <= up_drp_rdata_s;
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up_drp_ready <= up_drp_ready_s;
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up_drp_locked_m1 <= mmcm_locked_s;
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up_drp_locked <= up_drp_locked_m1;
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end
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end
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// instantiations
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generate
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if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin
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2017-04-20 15:43:37 +00:00
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MMCME2_ADV #(
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.BANDWIDTH ("OPTIMIZED"),
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.CLKOUT4_CASCADE ("FALSE"),
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.COMPENSATION ("ZHOLD"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (MMCM_VCO_DIV),
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.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
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.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
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.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
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.CLKOUT2_PHASE (MMCM_CLK2_PHASE),
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.CLKOUT2_DUTY_CYCLE (0.500),
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.CLKOUT2_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
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.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
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.REF_JITTER1 (0.010))
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i_mmcm (
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.CLKIN1 (clk),
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.CLKFBIN (bufg_fb_clk_s),
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.CLKFBOUT (mmcm_fb_clk_s),
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.CLKOUT0 (mmcm_clk_0_s),
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.CLKOUT1 (mmcm_clk_1_s),
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.CLKOUT2 (mmcm_clk_2_s),
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.LOCKED (mmcm_locked_s),
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.DCLK (up_clk),
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.DEN (up_drp_sel),
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.DADDR (up_drp_addr[6:0]),
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.DWE (up_drp_wr),
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.DI (up_drp_wdata),
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.DO (up_drp_rdata_s),
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.DRDY (up_drp_ready_s),
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.CLKFBOUTB (),
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.CLKOUT0B (),
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.CLKOUT1B (),
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.CLKOUT2B (),
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.CLKOUT3 (),
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.CLKOUT3B (),
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.CLKOUT4 (),
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.CLKOUT5 (),
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.CLKOUT6 (),
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.CLKIN2 (clk2),
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.CLKINSEL (clk_sel),
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE (),
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.CLKINSTOPPED (),
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.CLKFBSTOPPED (),
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.PWRDWN (1'b0),
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.RST (mmcm_rst));
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BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
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BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
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BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
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BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
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end else begin /* MMCM_DEVICE_TYPE == 1 */
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MMCM_ADV #(
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.BANDWIDTH ("OPTIMIZED"),
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.CLKOUT4_CASCADE ("FALSE"),
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.CLOCK_HOLD ("FALSE"),
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.COMPENSATION ("ZHOLD"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (MMCM_VCO_DIV),
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.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
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.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
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.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
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.CLKOUT2_PHASE (MMCM_CLK2_PHASE),
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.CLKOUT2_DUTY_CYCLE (0.500),
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.CLKOUT2_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
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.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
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.REF_JITTER1 (0.010))
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i_mmcm (
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.CLKIN1 (clk),
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.CLKFBIN (bufg_fb_clk_s),
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.CLKFBOUT (mmcm_fb_clk_s),
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.CLKOUT0 (mmcm_clk_0_s),
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.CLKOUT1 (mmcm_clk_1_s),
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.CLKOUT2 (mmcm_clk_2_s),
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.LOCKED (mmcm_locked_s),
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.DCLK (up_clk),
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.DEN (up_drp_sel),
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.DADDR (up_drp_addr[6:0]),
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.DWE (up_drp_wr),
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.DI (up_drp_wdata),
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.DO (up_drp_rdata_s),
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.DRDY (up_drp_ready_s),
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.CLKFBOUTB (),
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.CLKOUT0B (),
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.CLKOUT1B (),
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.CLKOUT2B (),
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.CLKOUT3 (),
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.CLKOUT3B (),
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.CLKOUT4 (),
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.CLKOUT5 (),
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.CLKOUT6 (),
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.CLKIN2 (clk2),
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.CLKINSEL (clk_sel),
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE (),
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.CLKINSTOPPED (),
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.CLKFBSTOPPED (),
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.PWRDWN (1'b0),
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.RST (mmcm_rst));
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BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
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BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
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BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
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BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
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2015-06-26 09:04:19 +00:00
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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