2015-06-26 09:04:19 +00:00
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# ip
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source ../scripts/adi_env.tcl
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2018-08-14 09:59:39 +00:00
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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2015-06-26 09:04:19 +00:00
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adi_ip_create axi_ad9671
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adi_ip_files axi_ad9671 [list \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/common/ad_pnmon.v" \
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"$ad_hdl_dir/library/common/ad_datafmt.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
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"$ad_hdl_dir/library/common/up_xfer_status.v" \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/ad_mem.v" \
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2016-12-08 21:02:40 +00:00
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"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
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2017-03-30 13:12:07 +00:00
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"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
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2015-06-26 09:04:19 +00:00
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"axi_ad9671_pnmon.v" \
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"axi_ad9671_channel.v" \
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"axi_ad9671_if.v" \
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2019-04-02 08:18:25 +00:00
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"axi_ad9671.v" ]
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2015-06-26 09:04:19 +00:00
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adi_ip_properties axi_ad9671
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2019-04-02 08:18:25 +00:00
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adi_init_bd_tcl
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2019-03-14 15:25:36 +00:00
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adi_ip_bd axi_ad9371 "bd/bd.tcl"
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2019-01-11 08:54:16 +00:00
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2021-10-20 15:08:35 +00:00
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set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9671} [ipx::current_core]
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2016-12-08 21:02:40 +00:00
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set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
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2015-06-26 09:04:19 +00:00
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set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]
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2019-01-11 08:54:16 +00:00
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adi_add_auto_fpga_spec_params
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ipx::create_xgui_files [ipx::current_core]
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2015-06-26 09:04:19 +00:00
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ipx::save_core [ipx::current_core]
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