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pluto_hdl_adi/library/axi_rd_wr_combiner/Makefile

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Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface The read and write interfaces of a AXI bus are independent other than that they use the same clock. Yet when connecting a single read-only and a single write-only interface to a Xilinx AXI interconnect it instantiates arbitration logic between the two interfaces. This is dead logic and unnecessarily utilizes the FPGAs resources. Introduce a new helper module that takes a read-only and a write-only AXI interface and combines them into a single read-write interface. The only restriction here is that all three interfaces need to use the same clock. This module is useful for systems which feature a read DMA and a write DMA. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-17 11:48:55 +00:00
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
hdlmake updates
2017-04-25 19:46:26 +00:00
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface The read and write interfaces of a AXI bus are independent other than that they use the same clock. Yet when connecting a single read-only and a single write-only interface to a Xilinx AXI interconnect it instantiates arbitration logic between the two interfaces. This is dead logic and unnecessarily utilizes the FPGAs resources. Introduce a new helper module that takes a read-only and a write-only AXI interface and combines them into a single read-write interface. The only restriction here is that all three interfaces need to use the same clock. This module is useful for systems which feature a read DMA and a write DMA. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-17 11:48:55 +00:00
M_DEPS += axi_rd_wr_combiner.v
hdlmake updates
2017-04-25 19:46:26 +00:00
M_DEPS += axi_rd_wr_combiner_ip.tcl
Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface The read and write interfaces of a AXI bus are independent other than that they use the same clock. Yet when connecting a single read-only and a single write-only interface to a Xilinx AXI interconnect it instantiates arbitration logic between the two interfaces. This is dead logic and unnecessarily utilizes the FPGAs resources. Introduce a new helper module that takes a read-only and a write-only AXI interface and combines them into a single read-write interface. The only restriction here is that all three interfaces need to use the same clock. This module is useful for systems which feature a read DMA and a write DMA. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-17 11:48:55 +00:00
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
hdlmake updates
2017-04-25 19:46:26 +00:00
.PHONY: all clean clean-all
all: axi_rd_wr_combiner.xpr
Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface The read and write interfaces of a AXI bus are independent other than that they use the same clock. Yet when connecting a single read-only and a single write-only interface to a Xilinx AXI interconnect it instantiates arbitration logic between the two interfaces. This is dead logic and unnecessarily utilizes the FPGAs resources. Introduce a new helper module that takes a read-only and a write-only AXI interface and combines them into a single read-write interface. The only restriction here is that all three interfaces need to use the same clock. This module is useful for systems which feature a read DMA and a write DMA. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-17 11:48:55 +00:00
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_rd_wr_combiner.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_rd_wr_combiner_ip.tcl >> axi_rd_wr_combiner_ip.log 2>&1
####################################################################################
####################################################################################