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pluto_hdl_adi/library/axi_fifo2s/axi_fifo2s_constr.xdc

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axi_fifo2s: added constraints
2014-10-14 15:55:16 +00:00
axi_fifo2s: include bus width/clock transfer
2014-11-11 20:25:35 +00:00
set_false_path -from [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
axi_fifo2s: added constraints
2014-10-14 15:55:16 +00:00