2016-09-21 09:28:06 +00:00
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# create a SPI Engine architecture
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2016-10-28 08:04:21 +00:00
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2016-09-21 09:28:06 +00:00
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create_bd_cell -type hier spi
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current_bd_instance /spi
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2016-10-28 08:04:21 +00:00
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir O irq
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create_bd_pin -dir O dma_clk
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2016-11-02 13:53:14 +00:00
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create_bd_pin -dir I dma_enable
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create_bd_pin -dir O dma_valid
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create_bd_pin -dir I -from 15 -to 0 dma_data
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create_bd_pin -dir I dma_xfer_req
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create_bd_pin -dir I dma_underflow
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2016-10-28 08:04:21 +00:00
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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2016-09-21 09:28:06 +00:00
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2017-04-28 07:12:05 +00:00
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ad_ip_instance spi_engine_execution execution
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ad_ip_instance axi_spi_engine axi
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ad_ip_instance axi_ad5766 axi_ad5766
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ad_ip_instance spi_engine_interconnect interconnect
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2016-09-21 09:28:06 +00:00
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2017-04-28 07:12:05 +00:00
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
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ad_ip_parameter interconnect CONFIG.NUM_OF_SDI 2
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2016-09-21 09:28:06 +00:00
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2016-10-28 08:04:21 +00:00
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ad_connect axi/spi_engine_offload_ctrl0 axi_ad5766/spi_engine_offload_ctrl
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ad_connect axi/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi_ad5766/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect m_spi execution/spi
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2016-11-02 13:53:14 +00:00
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ad_connect dma_data axi_ad5766/dma_data
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ad_connect dma_enable axi_ad5766/dma_enable
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ad_connect dma_valid axi_ad5766/dma_valid
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ad_connect dma_xfer_req axi_ad5766/dma_xfer_req
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ad_connect dma_underflow axi_ad5766/dma_underflow
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2016-09-21 09:28:06 +00:00
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2016-10-28 08:04:21 +00:00
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ad_connect clk execution/clk
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ad_connect clk axi/s_axi_aclk
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ad_connect clk axi_ad5766/s_axi_aclk
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ad_connect clk axi_ad5766/spi_clk
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ad_connect clk axi_ad5766/ctrl_clk
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ad_connect clk axi/spi_clk
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ad_connect clk interconnect/clk
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ad_connect dma_clk axi_ad5766/dma_clk
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2016-09-21 09:28:06 +00:00
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2016-10-28 08:04:21 +00:00
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ad_connect axi/spi_resetn axi_ad5766/spi_resetn
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ad_connect axi/spi_resetn execution/resetn
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ad_connect axi/spi_resetn interconnect/resetn
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2016-09-21 09:28:06 +00:00
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2016-10-28 08:04:21 +00:00
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ad_connect resetn axi/s_axi_aresetn
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ad_connect resetn axi_ad5766/s_axi_aresetn
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ad_connect irq axi/irq
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2016-09-21 09:28:06 +00:00
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current_bd_instance /
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ad_connect sys_cpu_clk spi/clk
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ad_connect sys_cpu_resetn spi/resetn
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
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ad_connect spi/m_spi spi
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2017-04-28 07:12:05 +00:00
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ad_ip_instance axi_dmac axi_ad5766_dac_dma
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ad_ip_parameter axi_ad5766_dac_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_ad5766_dac_dma CONFIG.DMA_TYPE_DEST 2
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ad_ip_parameter axi_ad5766_dac_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_ad5766_dac_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad5766_dac_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad5766_dac_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad5766_dac_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad5766_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 16
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2016-10-28 08:04:21 +00:00
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ad_connect spi/dma_clk axi_ad5766_dac_dma/fifo_rd_clk
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2016-11-02 13:53:14 +00:00
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ad_connect spi/dma_valid axi_ad5766_dac_dma/fifo_rd_en
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ad_connect spi/dma_xfer_req axi_ad5766_dac_dma/fifo_rd_xfer_req
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ad_connect spi/dma_data axi_ad5766_dac_dma/fifo_rd_dout
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ad_connect spi/dma_underflow axi_ad5766_dac_dma/fifo_rd_underflow
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ad_connect spi/dma_enable VCC
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2016-10-28 08:04:21 +00:00
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ad_cpu_interconnect 0x44a00000 spi/axi
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ad_cpu_interconnect 0x44a10000 spi/axi_ad5766
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ad_cpu_interconnect 0x44a20000 axi_ad5766_dac_dma
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk axi_ad5766_dac_dma/m_src_axi
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ad_connect sys_cpu_resetn axi_ad5766_dac_dma/m_src_axi_aresetn
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2016-09-21 09:28:06 +00:00
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2016-10-28 08:04:21 +00:00
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ad_cpu_interrupt ps-12 mb-13 spi/irq
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ad_cpu_interrupt ps-13 mb-12 axi_ad5766_dac_dma/irq
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2016-09-21 09:28:06 +00:00
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