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pluto_hdl_adi/projects/fmcomms8/a10soc/system_constr.sdc

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fmcomms8: a10soc: Initial commit
2020-08-31 14:52:10 +00:00
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
fmcomms8/intel: Fix fPLL configuration When phase alignment is active, the PFD frequency value should be used as outclk1 actual frequency. The configuration interface of the fPLL does not support fractional values. If the reference clock is fractional, the tool will throw an error that requirement above is not respected. Round up the reference clock for the SERDES and the lane rate in order to overcome this issue, until it's not fixed by Intel.
2021-01-12 09:19:13 +00:00
create_clock -period "4.06504065 ns" -name ref_clk_c [get_ports {ref_clk_c}]
create_clock -period "4.06504065 ns" -name ref_clk_d [get_ports {ref_clk_d}]
create_clock -period "4.06504065 ns" -name core_clk_c [get_ports {core_clk_c}]
create_clock -period "4.06504065 ns" -name core_clk_d [get_ports {core_clk_d}]
fmcomms8: a10soc: Initial commit
2020-08-31 14:52:10 +00:00
create_clock -period "100 ns" -name spi_clk [get_nets {i_system_bd|sys_spi|sys_spi|SCLK_reg}]
derive_pll_clocks
derive_clock_uncertainty
set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*]
set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*]
set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]