zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library/axi_adrv9001/axi_adrv9001_rx.v

418 lines
13 KiB
Coq
Raw Normal View History

library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
// ***************************************************************************
// ***************************************************************************
Add/edit copyright and license for .v, .sv files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 13:54:40 +00:00
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
Replace link in license header from master to main Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-12-13 16:03:34 +00:00
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adrv9001_rx #(
parameter ID = 0,
axi_adrv9001: Add opt-in synthesis parameters
2020-12-02 13:50:03 +00:00
parameter ENABLED = 1,
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
parameter CMOS_LVDS_N = 0,
parameter COMMON_BASE_ADDR = 'h00,
parameter CHANNEL_BASE_ADDR = 'h01,
parameter MODE_R1 = 1,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1
) (
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
// adc interface
output adc_rst,
input adc_clk,
input adc_valid_A,
input [ 15:0] adc_data_i_A,
input [ 15:0] adc_data_q_A,
input adc_valid_B,
input [ 15:0] adc_data_i_B,
input [ 15:0] adc_data_q_B,
output adc_single_lane,
output adc_sdr_ddr_n,
axi_adrv9001: Add support for symbol operation mode on Xilinx devices Add CMOS support for the interface for the following symbol modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 16/8 80(SDR)/160(DDR) 80 - SDR/DDR SDR/DDR->4/2(C=16), 2/1(C=8) Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface
2021-07-27 08:40:45 +00:00
output adc_symb_op,
output adc_symb_8_16b,
axi_adrv9001: Allow running Rx2/Tx2 channels in R1 mode without Rx1/Tx1 This commit removes the deadlock created while trying to use the Rx2/Tx2 channels without the Rx1/Tx1 channels enabled first.
2021-03-19 08:00:14 +00:00
output up_adc_r1_mode,
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks Depending on FPGA technology the physical layer uses different deserialization factors and corresponding clock division factors to divide the source synchronous interface clock. This must be exposed to software so it can act on it while setting the DDS rate. Xilinx CMOS clock ratio - 4 Xilinx LVDS clock ratio - 4 Intel CMOS clock ratio - 1
2021-03-10 09:21:55 +00:00
input [ 31:0] adc_clk_ratio,
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
// dac loopback interface
input dac_data_valid_A,
input [ 15:0] dac_data_i_A,
input [ 15:0] dac_data_q_A,
input dac_data_valid_B,
input [ 15:0] dac_data_i_B,
input [ 15:0] dac_data_q_B,
// dma interface
output adc_valid,
output adc_enable_i0,
output [ 15:0] adc_data_i0,
output adc_enable_q0,
output [ 15:0] adc_data_q0,
output adc_enable_i1,
output [ 15:0] adc_data_i1,
output adc_enable_q1,
output [ 15:0] adc_data_q1,
input adc_dovf,
axi_adrv9001: Add external sync support The external sync must be synchronous to the reference clock, in order to obtain a deterministic synchronization of the interface.
2021-12-03 14:40:48 +00:00
output adc_sync,
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack
);
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
generate
if (ENABLED == 0) begin : core_disabled
assign adc_rst = 1'b0;
assign adc_single_lane = 1'b0;
assign adc_sdr_ddr_n = 1'b0;
assign adc_symb_op = 1'b0;
assign adc_symb_8_16b = 1'b0;
assign up_adc_r1_mode = 1'b0;
assign adc_valid = 1'b0;
assign adc_enable_i0 = 1'b0;
assign adc_data_i0 = 16'b0;
assign adc_enable_q0 = 1'b0;
assign adc_data_q0 = 16'b0;
assign adc_enable_i1 = 1'b0;
assign adc_data_i1 = 16'b0;
assign adc_enable_q1 = 1'b0;
assign adc_data_q1 = 16'b0;
always @(*) begin
up_wack = 1'b0;
up_rdata = 32'b0;
up_rack = 1'b0;
end
axi_adrv9001: Add opt-in synthesis parameters
2020-12-02 13:50:03 +00:00
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
end else begin : core_enabled
// configuration settings
localparam CONFIG = (CMOS_LVDS_N * 128) +
(MODE_R1 * 16) +
(DATAFORMAT_DISABLE * 4) +
(DCFILTER_DISABLE * 2) +
(IQCORRECTION_DISABLE * 1);
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
// internal signals
wire [ 15:0] adc_data_iq_i0_s;
wire [ 15:0] adc_data_iq_q0_s;
wire [ 15:0] adc_data_iq_i1_s;
wire [ 15:0] adc_data_iq_q1_s;
wire [ 4:0] adc_num_lanes;
wire [ 3:0] up_adc_pn_err_s;
wire [ 3:0] up_adc_pn_oos_s;
wire [ 3:0] up_adc_or_s;
wire [ 4:0] up_wack_s;
wire [ 4:0] up_rack_s;
wire [ 31:0] up_rdata_s[0:4];
wire adc_valid_out_i0;
wire adc_valid_out_i1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_status_pn_err <= up_adc_r1_mode ? | up_adc_pn_err_s[1:0] : | up_adc_pn_err_s[3:0];
up_status_pn_oos <= up_adc_r1_mode ? | up_adc_pn_oos_s[1:0] : | up_adc_pn_oos_s[3:0];
up_status_or <= | up_adc_or_s;
up_wack <= | up_wack_s;
up_rack <= | up_rack_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4];
end
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
end
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
// channel width is 32 bits
assign adc_valid = adc_enable_i0 ? adc_valid_out_i0 : adc_valid_out_i1;
// channel 0 (i)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (0),
.COMMON_ID (CHANNEL_BASE_ADDR),
.DISABLE (0),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16)
) i_rx_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_A),
.adc_data_in (adc_data_i_A[15:0]),
.adc_valid_out (adc_valid_out_i0),
.adc_data_out (adc_data_i0),
.adc_data_iq_in (adc_data_iq_q0_s),
.adc_data_iq_out (adc_data_iq_i0_s),
.adc_enable (adc_enable_i0),
.dac_valid_in (dac_data_valid_A),
.dac_data_in (dac_data_i_A),
.up_adc_pn_err (up_adc_pn_err_s[0]),
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
.up_adc_or (up_adc_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel 1 (q)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (1),
.COMMON_ID (CHANNEL_BASE_ADDR),
.CHANNEL_ID (1),
.DISABLE (0),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16)
) i_rx_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_A),
.adc_data_in (adc_data_q_A[15:0]),
.adc_valid_out (),
.adc_data_out (adc_data_q0),
.adc_data_iq_in (adc_data_iq_i0_s),
.adc_data_iq_out (adc_data_iq_q0_s),
.adc_enable (adc_enable_q0),
.dac_valid_in (dac_data_valid_A),
.dac_data_in (dac_data_q_A),
.up_adc_pn_err (up_adc_pn_err_s[1]),
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
.up_adc_or (up_adc_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// channel 2 (i)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (0),
.COMMON_ID (CHANNEL_BASE_ADDR),
.CHANNEL_ID (2),
.DISABLE (MODE_R1),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16)
) i_rx_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_B),
.adc_data_in (adc_data_i_B[15:0]),
.adc_valid_out (adc_valid_out_i1),
.adc_data_out (adc_data_i1),
.adc_data_iq_in (adc_data_iq_q1_s),
.adc_data_iq_out (adc_data_iq_i1_s),
.adc_enable (adc_enable_i1),
.dac_valid_in (dac_data_valid_B),
.dac_data_in (dac_data_i_B),
.up_adc_pn_err (up_adc_pn_err_s[2]),
.up_adc_pn_oos (up_adc_pn_oos_s[2]),
.up_adc_or (up_adc_or_s[2]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// channel 3 (q)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (1),
.COMMON_ID (CHANNEL_BASE_ADDR),
.CHANNEL_ID (3),
.DISABLE (MODE_R1),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16)
) i_rx_channel_3 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_B),
.adc_data_in (adc_data_q_B[15:0]),
.adc_valid_out (),
.adc_data_out (adc_data_q1),
.adc_data_iq_in (adc_data_iq_i1_s),
.adc_data_iq_out (adc_data_iq_q1_s),
.adc_enable (adc_enable_q1),
.dac_valid_in (dac_data_valid_B),
.dac_data_in (dac_data_q_B),
.up_adc_pn_err (up_adc_pn_err_s[3]),
.up_adc_pn_oos (up_adc_pn_oos_s[3]),
.up_adc_or (up_adc_or_s[3]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// common processor control
up_adc_common #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.COMMON_ID (COMMON_BASE_ADDR),
.CONFIG(CONFIG),
.DRP_DISABLE(1),
.USERPORTS_DISABLE(1),
.GPIO_DISABLE(1),
.START_CODE_DISABLE(1)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_clk_ratio (adc_clk_ratio),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (adc_sync),
up_adc_common: Update IPs and adi_regmap_adc definition file to latest up_adc_common module
2022-09-29 05:26:51 +00:00
.adc_ext_sync_arm (),
.adc_ext_sync_disarm (),
.adc_ext_sync_manual_req (),
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
.adc_num_lanes (adc_num_lanes),
up_adc_common: Update IPs and adi_regmap_adc definition file to latest up_adc_common module
2022-09-29 05:26:51 +00:00
.adc_custom_control (),
.adc_crc_enable (),
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
.adc_sdr_ddr_n (adc_sdr_ddr_n),
.adc_symb_op (adc_symb_op),
.adc_symb_8_16b (adc_symb_8_16b),
.up_pps_rcounter(32'h0),
.up_pps_status(1'b0),
.up_pps_irq_mask(),
.up_adc_r1_mode (up_adc_r1_mode),
.up_adc_ce (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
Update IPs based on up_adc_common changes
2023-01-12 09:10:23 +00:00
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd3),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
assign adc_single_lane = adc_num_lanes[0];
axi_adrv9001: Add opt-in synthesis parameters
2020-12-02 13:50:03 +00:00
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
end
endgenerate
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
endmodule