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pluto_hdl_adi/library/axi_dmac/bd/bd.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
axi_dmac: Add support for auto-detecting asynchronous clock configuration Add support for querying the clock domains of the clock pins for the axi_dmac controller. This allows the core to automatically figure out whether its different parts run in different clock domains or not and setup the configuration parameters accordingly. Being able to auto-detect those configuration parameters makes the core easier to use and also avoids accidental misconfiguration. It is still possible to automatically overwrite the configuration parameters by hand if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 07:48:26 +00:00
proc init {cellpath otherInfo} {
axi_dmac: Use sane defaults for the AXI protocol type The axi_dmac core generates requests which are both AXI3 and AXI4 compliant. This means it is possible to connect it to both a AXI3 or AXI4 slave port without needing a AXI protocol converter. Unfortunately it is not possible to declare a port as both AXI3 and AXI4 compliant, so the core has the C_DMA_AXI_PROTCOL_SRC and C_DMA_AXI_PROTOCOL_DEST parameters, which allow to configure the protocol type of the corresponding AXI master interface. Currently the default is always AXI4. But when being used on ZYNQ it is most likely that the AXI master interface of the DMAC core ends up being connected to the AXI3, so change the default to AXI3 if the core is instantiated in a ZYNQ design. The default can still be overwritten by explicitly setting the configuration property. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 10:46:36 +00:00
set ip [get_bd_cells $cellpath]
bd::mark_propagate_override $ip \
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
"ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ ASYNC_CLK_REQ_SG ASYNC_CLK_SRC_SG ASYNC_CLK_DEST_SG"
axi_dmac: Use sane defaults for the AXI protocol type The axi_dmac core generates requests which are both AXI3 and AXI4 compliant. This means it is possible to connect it to both a AXI3 or AXI4 slave port without needing a AXI protocol converter. Unfortunately it is not possible to declare a port as both AXI3 and AXI4 compliant, so the core has the C_DMA_AXI_PROTCOL_SRC and C_DMA_AXI_PROTOCOL_DEST parameters, which allow to configure the protocol type of the corresponding AXI master interface. Currently the default is always AXI4. But when being used on ZYNQ it is most likely that the AXI master interface of the DMAC core ends up being connected to the AXI3, so change the default to AXI3 if the core is instantiated in a ZYNQ design. The default can still be overwritten by explicitly setting the configuration property. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 10:46:36 +00:00
axi_dmac: Add suport for 64 bit address width New improvements for the ADI DMAC IP: 1)The capability to manually overwrite the DMA_AXI_ADDR_WIDTH(from GUI or from tcl) 2)DMA_AXI_ADDR_WIDTH attribute is now visible in the Vivado GUI: -"Auto mode": Automatically calculated by the core tcl files based on the existing attached address segments. -"Manual mode": Specify the desired dma_width between 32-64 bits. 3)Added two new debug registers that return higher part of the current source/destination address. Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-09-14 11:28:34 +00:00
bd::mark_propagate_override $ip \
axi_dmac: Configure AXI address width according to the mapped address space Currently the AXI address width of the DMA is always 32-bit. But not all address spaces are so large that they require 32-bit to address all memory. Extract the size of the address space that the DMA is connected too and configure reduce the address size to the minimum required to address the full address space. This slightly reduces utilization. If no mapped address space can be found the default of 32 bits is used for the address. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-06 07:30:22 +00:00
"DMA_AXI_ADDR_WIDTH"
axi_dmac: Use sane defaults for the AXI protocol type The axi_dmac core generates requests which are both AXI3 and AXI4 compliant. This means it is possible to connect it to both a AXI3 or AXI4 slave port without needing a AXI protocol converter. Unfortunately it is not possible to declare a port as both AXI3 and AXI4 compliant, so the core has the C_DMA_AXI_PROTCOL_SRC and C_DMA_AXI_PROTOCOL_DEST parameters, which allow to configure the protocol type of the corresponding AXI master interface. Currently the default is always AXI4. But when being used on ZYNQ it is most likely that the AXI master interface of the DMAC core ends up being connected to the AXI3, so change the default to AXI3 if the core is instantiated in a ZYNQ design. The default can still be overwritten by explicitly setting the configuration property. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 10:46:36 +00:00
# On ZYNQ the core is most likely connected to the AXI3 HP ports so use AXI3
# as the default.
set family [string tolower [get_property FAMILY [get_property PART [current_project]]]]
if {$family == "zynq"} {
set axi_protocol 1
} else {
set axi_protocol 0
}
axi_dmac: Add validation values to IPI package Add validation values for the different configuration parameters. This enables the tools to check whether the configured value is valid and avoids accidental misconfiguration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:53:54 +00:00
foreach dir {SRC DEST} {
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
# Change the protocol by first enabling the parameter - setting the type to AXI MM
axi_dmac: Add validation values to IPI package Add validation values for the different configuration parameters. This enables the tools to check whether the configured value is valid and avoids accidental misconfiguration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:53:54 +00:00
set old [get_property "CONFIG.DMA_TYPE_${dir}" $ip]
set_property "CONFIG.DMA_TYPE_${dir}" "0" $ip
set_property "CONFIG.DMA_AXI_PROTOCOL_${dir}" $axi_protocol $ip
set_property "CONFIG.DMA_TYPE_${dir}" $old $ip
}
axi_dmac: burst_memory: Add support for using asymmetric memory FPGAs support different widths for the read and write port of the block SRAM cells. The DMAC can make use of this feature when the source and destination interface have a different width to up-size/down-size the data bus. Using memory cells with asymmetric port width consumes the same amount of SRAM cells, but allows to bypass the re-size blocks inside the DMAC that are otherwise used for up- and down-sizing. This reduces overall resource usage and can improve timing. If the ratio between the destination and source port is too larger to be handled by SRAM alone the SRAM block will be configured to do partial up- or down-sizing and a resize block will be inserted to take care of the remaining up-/down-sizing. E.g. if a 256-bit interface is connected to a 32-bit interface the SRAM will be used to do an initial resizing of 256 bit to 64 bit and a resize block will be used to do the remaining resizing from 64 bit to 32 bit. Currently this feature is disabled for Intel FPGAs since Quartus does not properly infer a block RAM with different read and write port widths from the current ad_asym_mem module. Once that has been resolved support for asymmetric memories can also be enabled in the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-08 09:43:43 +00:00
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
# Change the protocol by first enabling the parameter - enabling the SG transfers
set old [get_property "CONFIG.DMA_SG_TRANSFER" $ip]
set_property "CONFIG.DMA_SG_TRANSFER" "true" $ip
set_property "CONFIG.DMA_AXI_PROTOCOL_SG" $axi_protocol $ip
set_property "CONFIG.DMA_SG_TRANSFER" $old $ip
axi_dmac: burst_memory: Add support for using asymmetric memory FPGAs support different widths for the read and write port of the block SRAM cells. The DMAC can make use of this feature when the source and destination interface have a different width to up-size/down-size the data bus. Using memory cells with asymmetric port width consumes the same amount of SRAM cells, but allows to bypass the re-size blocks inside the DMAC that are otherwise used for up- and down-sizing. This reduces overall resource usage and can improve timing. If the ratio between the destination and source port is too larger to be handled by SRAM alone the SRAM block will be configured to do partial up- or down-sizing and a resize block will be inserted to take care of the remaining up-/down-sizing. E.g. if a 256-bit interface is connected to a 32-bit interface the SRAM will be used to do an initial resizing of 256 bit to 64 bit and a resize block will be used to do the remaining resizing from 64 bit to 32 bit. Currently this feature is disabled for Intel FPGAs since Quartus does not properly infer a block RAM with different read and write port widths from the current ad_asym_mem module. Once that has been resolved support for asymmetric memories can also be enabled in the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-08 09:43:43 +00:00
# Versions earlier than 2017.3 infer sub-optimal asymmetric memory
# See https://www.xilinx.com/support/answers/69179.html
axi_dmac: generalize version check In some cases, the Vivado version can contain other characters than just numbers. One such example is after applying the patch of AR# 71948, which makes `version -short` return something like `2018.3_AR71948`. This patch changes the version check to ignore anything after the first two components of the version.
2020-04-02 07:30:36 +00:00
regexp {^[0-9]+\.[0-9]+} [version -short] short_version
if {[expr $short_version > 2017.2]} {
axi_dmac: burst_memory: Add support for using asymmetric memory FPGAs support different widths for the read and write port of the block SRAM cells. The DMAC can make use of this feature when the source and destination interface have a different width to up-size/down-size the data bus. Using memory cells with asymmetric port width consumes the same amount of SRAM cells, but allows to bypass the re-size blocks inside the DMAC that are otherwise used for up- and down-sizing. This reduces overall resource usage and can improve timing. If the ratio between the destination and source port is too larger to be handled by SRAM alone the SRAM block will be configured to do partial up- or down-sizing and a resize block will be inserted to take care of the remaining up-/down-sizing. E.g. if a 256-bit interface is connected to a 32-bit interface the SRAM will be used to do an initial resizing of 256 bit to 64 bit and a resize block will be used to do the remaining resizing from 64 bit to 32 bit. Currently this feature is disabled for Intel FPGAs since Quartus does not properly infer a block RAM with different read and write port widths from the current ad_asym_mem module. Once that has been resolved support for asymmetric memories can also be enabled in the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-08 09:43:43 +00:00
set_property "CONFIG.ALLOW_ASYM_MEM" 1 $ip
}
axi_dmac: Add support for auto-detecting asynchronous clock configuration Add support for querying the clock domains of the clock pins for the axi_dmac controller. This allows the core to automatically figure out whether its different parts run in different clock domains or not and setup the configuration parameters accordingly. Being able to auto-detect those configuration parameters makes the core easier to use and also avoids accidental misconfiguration. It is still possible to automatically overwrite the configuration parameters by hand if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 07:48:26 +00:00
}
axi_dmac: Configure AXI master bus properties according to core configuration Configure the maximum burst size as well as the maximum number of active requests on the AXI master interfaces according to the core configuration. This allows connected slaves to know what kind of requests to expect and allows them to configure themselves accordingly. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 09:46:44 +00:00
proc post_config_ip {cellpath otherinfo} {
set ip [get_bd_cells $cellpath]
# Update AXI interface properties according to configuration
set max_bytes_per_burst [get_property "CONFIG.MAX_BYTES_PER_BURST" $ip]
set fifo_size [get_property "CONFIG.FIFO_SIZE" $ip]
foreach dir {"SRC" "DEST"} {
set type [get_property "CONFIG.DMA_TYPE_$dir" $ip]
if {$type != 0} {
continue
}
axi_dmac: Limit MAX_BYTES_PER_BURST to maximum supported value The MAX_BYTES_PER_BURST option allows to configure the maximum bytes that are part of a burst. This can be an arbitrary value. At the same time there is a limit of how many bytes can be supported by the memory buses. A AXI3 interface supports a maximum of 16 beats per burst and a AXI4 interface supports a maximum of 256 beats per burst. At the moment the it is possible to specify a MAX_BYTES_PER_BURST value that exceeds what can be supported by the AXI memory-mapped bus. If that is the case undefined behavior will occur and the DMAC will function incorrectly. To avoid this make sure that the MAX_BYTES_PER_BURST value does not exceed the maximum that can be supported by the interfaces. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-23 14:49:07 +00:00
set axi_protocol [get_property "CONFIG.DMA_AXI_PROTOCOL_$dir" $ip]
axi_dmac: Configure AXI master bus properties according to core configuration Configure the maximum burst size as well as the maximum number of active requests on the AXI master interfaces according to the core configuration. This allows connected slaves to know what kind of requests to expect and allows them to configure themselves accordingly. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 09:46:44 +00:00
set data_width [get_property "CONFIG.DMA_DATA_WIDTH_$dir" $ip]
set max_beats_per_burst [expr {int(ceil($max_bytes_per_burst * 8.0 / $data_width))}]
axi_dmac: Limit MAX_BYTES_PER_BURST to maximum supported value The MAX_BYTES_PER_BURST option allows to configure the maximum bytes that are part of a burst. This can be an arbitrary value. At the same time there is a limit of how many bytes can be supported by the memory buses. A AXI3 interface supports a maximum of 16 beats per burst and a AXI4 interface supports a maximum of 256 beats per burst. At the moment the it is possible to specify a MAX_BYTES_PER_BURST value that exceeds what can be supported by the AXI memory-mapped bus. If that is the case undefined behavior will occur and the DMAC will function incorrectly. To avoid this make sure that the MAX_BYTES_PER_BURST value does not exceed the maximum that can be supported by the interfaces. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-23 14:49:07 +00:00
if {$axi_protocol == 0} {
set axi_protocol_str "AXI4"
if {$max_beats_per_burst > 256} {
set max_beats_per_burst 256
}
} else {
set axi_protocol_str "AXI3"
if {$max_beats_per_burst > 16} {
set max_beats_per_burst 16
}
}
axi_dmac: Configure AXI master bus properties according to core configuration Configure the maximum burst size as well as the maximum number of active requests on the AXI master interfaces according to the core configuration. This allows connected slaves to know what kind of requests to expect and allows them to configure themselves accordingly. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 09:46:44 +00:00
set intf [get_bd_intf_pins [format "%s/m_%s_axi" $cellpath [string tolower $dir]]]
axi_dmac: Limit MAX_BYTES_PER_BURST to maximum supported value The MAX_BYTES_PER_BURST option allows to configure the maximum bytes that are part of a burst. This can be an arbitrary value. At the same time there is a limit of how many bytes can be supported by the memory buses. A AXI3 interface supports a maximum of 16 beats per burst and a AXI4 interface supports a maximum of 256 beats per burst. At the moment the it is possible to specify a MAX_BYTES_PER_BURST value that exceeds what can be supported by the AXI memory-mapped bus. If that is the case undefined behavior will occur and the DMAC will function incorrectly. To avoid this make sure that the MAX_BYTES_PER_BURST value does not exceed the maximum that can be supported by the interfaces. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-23 14:49:07 +00:00
set_property CONFIG.PROTOCOL $axi_protocol_str $intf
axi_dmac: Configure AXI master bus properties according to core configuration Configure the maximum burst size as well as the maximum number of active requests on the AXI master interfaces according to the core configuration. This allows connected slaves to know what kind of requests to expect and allows them to configure themselves accordingly. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 09:46:44 +00:00
set_property CONFIG.MAX_BURST_LENGTH $max_beats_per_burst $intf
# The core issues as many requests as the amount of data the FIFO can hold
if {$dir == "SRC"} {
set_property CONFIG.NUM_WRITE_OUTSTANDING 0 $intf
set_property CONFIG.NUM_READ_OUTSTANDING $fifo_size $intf
} else {
set_property CONFIG.NUM_WRITE_OUTSTANDING $fifo_size $intf
set_property CONFIG.NUM_READ_OUTSTANDING 0 $intf
}
}
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
# SG interface configuration
set sg_enabled [get_property CONFIG.DMA_SG_TRANSFER $ip]
if {$sg_enabled == "true"} {
set axi_protocol [get_property "CONFIG.DMA_AXI_PROTOCOL_SG" $ip]
if {$axi_protocol == 0} {
set axi_protocol_str "AXI4"
set max_beats_per_burst 256
} else {
set axi_protocol_str "AXI3"
set max_beats_per_burst 16
}
set intf [get_bd_intf_pins [format "%s/m_sg_axi" $cellpath]]
set_property CONFIG.PROTOCOL $axi_protocol_str $intf
set_property CONFIG.MAX_BURST_LENGTH $max_beats_per_burst $intf
set_property CONFIG.NUM_WRITE_OUTSTANDING 0 $intf
set_property CONFIG.NUM_READ_OUTSTANDING 0 $intf
}
axi_dmac: Configure AXI master bus properties according to core configuration Configure the maximum burst size as well as the maximum number of active requests on the AXI master interfaces according to the core configuration. This allows connected slaves to know what kind of requests to expect and allows them to configure themselves accordingly. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 09:46:44 +00:00
}
axi_dmac: Add support for auto-detecting asynchronous clock configuration Add support for querying the clock domains of the clock pins for the axi_dmac controller. This allows the core to automatically figure out whether its different parts run in different clock domains or not and setup the configuration parameters accordingly. Being able to auto-detect those configuration parameters makes the core easier to use and also avoids accidental misconfiguration. It is still possible to automatically overwrite the configuration parameters by hand if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 07:48:26 +00:00
proc axi_dmac_detect_async_clk { cellpath ip param_name clk_a clk_b } {
set param_src [get_property "CONFIG.$param_name.VALUE_SRC" $ip]
if {[string equal $param_src "USER"]} {
return;
}
set clk_domain_a [get_property CONFIG.CLK_DOMAIN $clk_a]
set clk_domain_b [get_property CONFIG.CLK_DOMAIN $clk_b]
set clk_freq_a [get_property CONFIG.FREQ_HZ $clk_a]
set clk_freq_b [get_property CONFIG.FREQ_HZ $clk_b]
set clk_phase_a [get_property CONFIG.PHASE $clk_a]
set clk_phase_b [get_property CONFIG.PHASE $clk_b]
# Only mark it as sync if we can make sure that it is sync, if the
# relationship of the clocks is unknown mark it as async
if {$clk_domain_a != {} && $clk_domain_b != {} && \
$clk_domain_a == $clk_domain_b && $clk_freq_a == $clk_freq_b && \
$clk_phase_a == $clk_phase_b} {
set clk_async 0
} else {
set clk_async 1
}
set_property "CONFIG.$param_name" $clk_async $ip
# if {$clk_async == 0} {
# bd::send_msg -of $cellpath -type INFO -msg_id 1 -text "$clk_a and $clk_b are synchronous"
# } else {
# bd::send_msg -of $cellpath -type INFO -msg_id 1 -text "$clk_a and $clk_b are asynchronous"
# }
}
proc propagate {cellpath otherinfo} {
set ip [get_bd_cells $cellpath]
set src_type [get_property CONFIG.DMA_TYPE_SRC $ip]
set dest_type [get_property CONFIG.DMA_TYPE_DEST $ip]
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
set sg_enabled [get_property CONFIG.DMA_SG_TRANSFER $ip]
axi_dmac: Add support for auto-detecting asynchronous clock configuration Add support for querying the clock domains of the clock pins for the axi_dmac controller. This allows the core to automatically figure out whether its different parts run in different clock domains or not and setup the configuration parameters accordingly. Being able to auto-detect those configuration parameters makes the core easier to use and also avoids accidental misconfiguration. It is still possible to automatically overwrite the configuration parameters by hand if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 07:48:26 +00:00
set req_clk [get_bd_pins "$ip/s_axi_aclk"]
if {$src_type == 2} {
set src_clk [get_bd_pins "$ip/fifo_wr_clk"]
} elseif {$src_type == 1} {
set src_clk [get_bd_pins "$ip/s_axis_aclk"]
} else {
set src_clk [get_bd_pins "$ip/m_src_axi_aclk"]
}
if {$dest_type == 2} {
set dest_clk [get_bd_pins "$ip/fifo_rd_clk"]
axi_dmac: Fix typo on ./bd/bd.tcl
2015-09-23 12:51:50 +00:00
} elseif {$dest_type == 1} {
axi_dmac: Add support for auto-detecting asynchronous clock configuration Add support for querying the clock domains of the clock pins for the axi_dmac controller. This allows the core to automatically figure out whether its different parts run in different clock domains or not and setup the configuration parameters accordingly. Being able to auto-detect those configuration parameters makes the core easier to use and also avoids accidental misconfiguration. It is still possible to automatically overwrite the configuration parameters by hand if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 07:48:26 +00:00
set dest_clk [get_bd_pins "$ip/m_axis_aclk"]
} else {
set dest_clk [get_bd_pins "$ip/m_dest_axi_aclk"]
}
axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_REQ_SRC" $req_clk $src_clk
axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_SRC_DEST" $src_clk $dest_clk
axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_DEST_REQ" $dest_clk $req_clk
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
if {$sg_enabled == "true"} {
set sg_clk [get_bd_pins "$ip/m_sg_axi_aclk"]
axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_REQ_SG" $req_clk $sg_clk
axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_SRC_SG" $src_clk $sg_clk
axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_DEST_SG" $dest_clk $sg_clk
}
axi_dmac: Add support for auto-detecting asynchronous clock configuration Add support for querying the clock domains of the clock pins for the axi_dmac controller. This allows the core to automatically figure out whether its different parts run in different clock domains or not and setup the configuration parameters accordingly. Being able to auto-detect those configuration parameters makes the core easier to use and also avoids accidental misconfiguration. It is still possible to automatically overwrite the configuration parameters by hand if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 07:48:26 +00:00
}
axi_dmac: Configure AXI address width according to the mapped address space Currently the AXI address width of the DMA is always 32-bit. But not all address spaces are so large that they require 32-bit to address all memory. Extract the size of the address space that the DMA is connected too and configure reduce the address size to the minimum required to address the full address space. This slightly reduces utilization. If no mapped address space can be found the default of 32 bits is used for the address. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-06 07:30:22 +00:00
proc post_propagate {cellpath otherinfo} {
set ip [get_bd_cells $cellpath]
set addr_width 16
foreach dir {"SRC" "DEST"} {
set type [get_property "CONFIG.DMA_TYPE_$dir" $ip]
if {$type != 0} {
continue
}
set intf [get_bd_intf_pins [format "%s/m_%s_axi" $cellpath [string tolower $dir]]]
axi_dmac: post_propagate(): Handle mappings with multiple address segments When a mapping has multiple address segments we need to consider all of them to calculate the required address width. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 11:05:44 +00:00
set addr_segs [get_bd_addr_segs -of_objects [get_bd_addr_spaces $intf]]
if {$addr_segs != {}} {
foreach addr_seg $addr_segs {
set range [get_property "range" $addr_seg]
set offset [get_property "offset" $addr_seg]
axi_dmac: fix address width detection The round function from tcl is a rounding to nearest. Using it in address width calculation produces incorrect values. e.g. round(log(0xAF000000)/log(2)) will produce 31 instead of 32 The fix is to replace the rounding function with ceiling that guarantees rounding up.
2018-07-20 06:44:04 +00:00
set addr_width [expr max(int(ceil(log($range - 1 + $offset) / log(2))), $addr_width)]
axi_dmac: post_propagate(): Handle mappings with multiple address segments When a mapping has multiple address segments we need to consider all of them to calculate the required address width. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 11:05:44 +00:00
}
axi_dmac: Configure AXI address width according to the mapped address space Currently the AXI address width of the DMA is always 32-bit. But not all address spaces are so large that they require 32-bit to address all memory. Extract the size of the address space that the DMA is connected too and configure reduce the address size to the minimum required to address the full address space. This slightly reduces utilization. If no mapped address space can be found the default of 32 bits is used for the address. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-06 07:30:22 +00:00
} else {
set addr_width 32
}
}
set_property "CONFIG.DMA_AXI_ADDR_WIDTH" $addr_width $ip
}