pluto_hdl_adi/library/axi_dmac/response_generator.v

// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
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// The user should read each of these license terms, and understand the
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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//      This will allow to generate bit files and not release the source code,
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module response_generator #(

  parameter ID_WIDTH = 3
) (
  input clk,
  input resetn,

  input enable,
  output reg enabled,

  input [ID_WIDTH-1:0] request_id,
  output reg [ID_WIDTH-1:0] response_id,

  input eot,

  output resp_valid,
  input resp_ready,
  output resp_eot,
  output [1:0] resp_resp
);

`include "inc_id.vh"
`include "resp.vh"

  assign resp_resp = RESP_OKAY;
  assign resp_eot = eot;

  assign resp_valid = request_id != response_id && enabled;

  // We have to wait for all responses before we can disable the response handler
  always @(posedge clk) begin
    if (resetn == 1'b0) begin
      enabled <= 1'b0;
    end else if (enable == 1'b1) begin
      enabled <= 1'b1;
    end else if (request_id == response_id) begin
      enabled <= 1'b0;
    end
  end

  always @(posedge clk) begin
    if (resetn == 1'b0) begin
      response_id <= 'h0;
    end else if (resp_valid == 1'b1 && resp_ready == 1'b1) begin
      response_id <= inc_id(response_id);
    end
  end

endmodule