301 lines
10 KiB
Tcl
301 lines
10 KiB
Tcl
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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proc load_fir_filter_vector {filter_file} {
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set fp [open $filter_file r]
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set data [split [read $fp] "\n"]
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set filter ""
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close $fp
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foreach line $data {
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set line [string trim $line]
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if {[string equal -length 1 $line "#"] || $line eq ""} {
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continue
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}
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if {$filter ne ""} {
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append filter ","
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}
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append filter $line
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}
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return $filter
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}
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {35}] $sys_ps7
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set_property LEFT 34 [get_bd_ports GPIO_I]
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set_property LEFT 34 [get_bd_ports GPIO_O]
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set_property LEFT 34 [get_bd_ports GPIO_T]
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set axi_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_dma]
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set_property -dict [list \
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CONFIG.C_FIFO_SIZE 2 \
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CONFIG.C_DMA_TYPE_SRC 2 \
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CONFIG.C_DMA_TYPE_DEST 0 \
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CONFIG.C_CYCLIC 0 \
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CONFIG.C_SYNC_TRANSFER_START 1 \
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CONFIG.C_AXI_SLICE_SRC 0 \
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CONFIG.C_AXI_SLICE_DEST 0 \
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CONFIG.C_CLKS_ASYNC_DEST_REQ 0 \
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CONFIG.C_CLKS_ASYNC_SRC_DEST 0 \
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CONFIG.C_CLKS_ASYNC_REQ_SRC 0 \
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CONFIG.C_2D_TRANSFER 0 \
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CONFIG.C_DMA_DATA_WIDTH_SRC 32 \
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CONFIG.C_DMA_DATA_WIDTH_DEST 64 \
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CONFIG.C_DMA_AXI_PROTOCOL_DEST 1 \
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] $axi_dma
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# Create SPI engine controller with offload
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create_bd_cell -type hier spi
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current_bd_instance /spi
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir O conv_done
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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set spi_engine [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_execution:1.0 execution]
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set axi_spi_engine [create_bd_cell -type ip -vlnv analog.com:user:axi_spi_engine:1.0 axi]
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set spi_engine_offload [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_offload:1.0 offload]
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set spi_engine_interconnect [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_interconnect:1.0 interconnect]
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set util_sigma_delta_spi [create_bd_cell -type ip -vlnv analog.com:user:util_sigma_delta_spi:1.0 util_sigma_delta_spi]
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set_property -dict [list CONFIG.NUM_CS 2] $spi_engine
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set_property -dict [list CONFIG.NUM_CS 2] $util_sigma_delta_spi
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ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi M_AXIS_SAMPLE
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ad_connect util_sigma_delta_spi/data_ready offload/trigger
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ad_connect util_sigma_delta_spi/data_ready conv_done
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ad_connect execution/active util_sigma_delta_spi/spi_active
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ad_connect execution/spi util_sigma_delta_spi/s_spi
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ad_connect util_sigma_delta_spi/m_spi m_spi
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connect_bd_net \
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[get_bd_pins clk] \
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[get_bd_pins offload/spi_clk] \
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[get_bd_pins offload/ctrl_clk] \
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[get_bd_pins execution/clk] \
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[get_bd_pins axi/s_axi_aclk] \
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[get_bd_pins axi/spi_clk] \
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[get_bd_pins interconnect/clk] \
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[get_bd_pins util_sigma_delta_spi/clk]
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connect_bd_net \
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[get_bd_pins axi/spi_resetn] \
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[get_bd_pins offload/spi_resetn] \
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[get_bd_pins execution/resetn] \
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[get_bd_pins interconnect/resetn] \
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[get_bd_pins util_sigma_delta_spi/resetn]
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connect_bd_net [get_bd_pins resetn] [get_bd_pins axi/s_axi_aresetn]
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ad_connect irq axi/irq
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current_bd_instance /
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
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ad_connect spi/m_spi spi
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set phase_gen [create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 phase_gen]
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set phase_slice [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 phase_slice]
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create_bd_port -dir O excitation
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set excitation_freq 1020
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set_property -dict [list \
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CONFIG.Output_Width 32 \
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CONFIG.Increment_Value [format "%x" [expr $excitation_freq * (1<<32) / 100000000]] \
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] $phase_gen
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set_property -dict [list \
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CONFIG.DIN_TO {31} \
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CONFIG.DIN_FROM {31} \
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CONFIG.DOUT_WIDTH {1} \
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] $phase_slice
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ad_connect /phase_gen/Q /phase_slice/Din
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ad_connect /phase_slice/Dout excitation
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create_bd_cell -type hier processing
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current_bd_instance /processing
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I conv_done
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create_bd_pin -dir I -from 31 -to 0 phase
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create_bd_pin -dir O overflow
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create_bd_pin -dir I -from 13 -to 0 channel_enable
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_SAMPLE
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:fifo_wr_rtl:1.0 DMA_WR
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create_bd_cell -type ip -vlnv analog.com:user:cn0363_phase_data_sync:1.0 phase_data_sync
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create_bd_cell -type ip -vlnv analog.com:user:cn0363_dma_sequencer:1.0 sequencer
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create_bd_cell -type ip -vlnv analog.com:user:cordic_demod:1.0 cordic_demod
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create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 phase_broadcast
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create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_broadcast
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create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_filtered_broadcast
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create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 i_q_broadcast
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create_bd_cell -type ip -vlnv xilinx.com:ip:axis_combiner:1.1 phase_sample_combine
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set i_q_resize [create_bd_cell -type ip -vlnv analog.com:user:util_axis_resize:1.0 i_q_resize]
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set_property -dict [list \
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CONFIG.C_M_DATA_WIDTH 32 \
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CONFIG.C_S_DATA_WIDTH 64 \
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] $i_q_resize
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set hpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 hpf]
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set lpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 lpf]
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set_property -dict [list \
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CONFIG.Data_Fractional_Bits.VALUE_SRC USER \
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CONFIG.Data_Sign.VALUE_SRC USER \
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||
|
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CONFIG.Data_Width.VALUE_SRC USER \
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||
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|
CONFIG.M_DATA_Has_TREADY true \
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||
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|
CONFIG.Number_Channels 2 \
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||
|
|
CONFIG.Sample_Frequency 0.025 \
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||
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|
CONFIG.Clock_Frequency 100 \
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||
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CONFIG.Coefficient_Width 16 \
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||
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CONFIG.Data_Width 24 \
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CONFIG.Output_Width 32 \
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CONFIG.Output_Rounding_Mode Truncate_LSBs \
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CONFIG.Has_ARESETn true \
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CONFIG.Reset_Data_Vector false \
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||
|
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CONFIG.CoefficientVector [load_fir_filter_vector "filters/hpf.mat"] \
|
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] $hpf
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||
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|
set_property -dict [list \
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||
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CONFIG.Data_Fractional_Bits.VALUE_SRC USER \
|
||
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CONFIG.Data_Sign.VALUE_SRC USER \
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||
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CONFIG.Data_Width.VALUE_SRC USER \
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CONFIG.M_DATA_Has_TREADY true \
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||
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CONFIG.Number_Channels 4 \
|
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CONFIG.Sample_Frequency 0.025 \
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||
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|
CONFIG.Clock_Frequency 100 \
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||
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CONFIG.Coefficient_Width 24 \
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CONFIG.Data_Width 32 \
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||
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CONFIG.Output_Width 32 \
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||
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CONFIG.Output_Rounding_Mode Truncate_LSBs \
|
||
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|
CONFIG.Has_ARESETn true \
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||
|
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CONFIG.Reset_Data_Vector false \
|
||
|
|
CONFIG.CoefficientVector [load_fir_filter_vector "filters/lpf.mat"] \
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] $lpf
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||
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|
||
|
|
set overflow_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 overflow_or]
|
||
|
|
set_property -dict [list \
|
||
|
|
CONFIG.C_SIZE 1 \
|
||
|
|
CONFIG.C_OPERATION {or} \
|
||
|
|
] $overflow_or
|
||
|
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|
||
|
|
ad_connect S_AXIS_SAMPLE phase_data_sync/S_AXIS_SAMPLE
|
||
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|
ad_connect conv_done phase_data_sync/conv_done
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||
|
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ad_connect phase phase_data_sync/phase
|
||
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|
||
|
|
ad_connect phase_data_sync/M_AXIS_PHASE phase_broadcast/S_AXIS
|
||
|
|
ad_connect phase_broadcast/M00_AXIS sequencer/phase
|
||
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ad_connect phase_broadcast/M01_AXIS phase_sample_combine/S01_AXIS
|
||
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|
||
|
|
ad_connect phase_data_sync/M_AXIS_SAMPLE sample_broadcast/S_AXIS
|
||
|
|
ad_connect sample_broadcast/M00_AXIS sequencer/data
|
||
|
|
ad_connect sample_broadcast/M01_AXIS hpf/S_AXIS_DATA
|
||
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|
||
|
|
ad_connect hpf/M_AXIS_DATA sample_filtered_broadcast/S_AXIS
|
||
|
|
ad_connect sample_filtered_broadcast/M00_AXIS sequencer/data_filtered
|
||
|
|
ad_connect sample_filtered_broadcast/M01_AXIS phase_sample_combine/S00_AXIS
|
||
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|
||
|
|
ad_connect phase_sample_combine/M_AXIS cordic_demod/S_AXIS
|
||
|
|
ad_connect cordic_demod/M_AXIS i_q_resize/s_axis
|
||
|
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|
||
|
|
ad_connect i_q_resize/m_axis i_q_broadcast/S_AXIS
|
||
|
|
ad_connect i_q_broadcast/M00_AXIS sequencer/i_q
|
||
|
|
ad_connect i_q_broadcast/M01_AXIS lpf/S_AXIS_DATA
|
||
|
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|
||
|
|
ad_connect lpf/M_AXIS_DATA sequencer/i_q_filtered
|
||
|
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|
||
|
|
connect_bd_net \
|
||
|
|
[get_bd_pins clk] \
|
||
|
|
[get_bd_pins phase_data_sync/clk] \
|
||
|
|
[get_bd_pins sequencer/clk] \
|
||
|
|
[get_bd_pins cordic_demod/clk] \
|
||
|
|
[get_bd_pins phase_broadcast/aclk] \
|
||
|
|
[get_bd_pins sample_broadcast/aclk] \
|
||
|
|
[get_bd_pins sample_filtered_broadcast/aclk] \
|
||
|
|
[get_bd_pins i_q_broadcast/aclk] \
|
||
|
|
[get_bd_pins phase_sample_combine/aclk] \
|
||
|
|
[get_bd_pins i_q_resize/clk] \
|
||
|
|
[get_bd_pins hpf/aclk] \
|
||
|
|
[get_bd_pins lpf/aclk]
|
||
|
|
|
||
|
|
connect_bd_net \
|
||
|
|
[get_bd_pins resetn] \
|
||
|
|
[get_bd_pins sequencer/resetn] \
|
||
|
|
[get_bd_pins phase_data_sync/resetn] \
|
||
|
|
|
||
|
|
connect_bd_net \
|
||
|
|
[get_bd_pins sequencer/processing_resetn] \
|
||
|
|
[get_bd_pins phase_data_sync/processing_resetn] \
|
||
|
|
[get_bd_pins cordic_demod/resetn] \
|
||
|
|
[get_bd_pins phase_broadcast/aresetn] \
|
||
|
|
[get_bd_pins sample_broadcast/aresetn] \
|
||
|
|
[get_bd_pins sample_filtered_broadcast/aresetn] \
|
||
|
|
[get_bd_pins i_q_broadcast/aresetn] \
|
||
|
|
[get_bd_pins phase_sample_combine/aresetn] \
|
||
|
|
[get_bd_pins i_q_resize/resetn] \
|
||
|
|
[get_bd_pins hpf/aresetn] \
|
||
|
|
[get_bd_pins lpf/aresetn]
|
||
|
|
|
||
|
|
ad_connect channel_enable sequencer/channel_enable
|
||
|
|
ad_connect sequencer/dma_wr DMA_WR
|
||
|
|
|
||
|
|
ad_connect phase_data_sync/overflow overflow_or/Op1
|
||
|
|
ad_connect sequencer/overflow overflow_or/Op2
|
||
|
|
ad_connect overflow_or/Res overflow
|
||
|
|
|
||
|
|
ad_connect phase_data_sync/sample_has_stat GND
|
||
|
|
|
||
|
|
current_bd_instance /
|
||
|
|
|
||
|
|
ad_connect /spi/M_AXIS_SAMPLE /processing/S_AXIS_SAMPLE
|
||
|
|
ad_connect /spi/conv_done /processing/conv_done
|
||
|
|
ad_connect /phase_gen/Q /processing/phase
|
||
|
|
|
||
|
|
set axi_adc [create_bd_cell -type ip -vlnv analog.com:user:axi_generic_adc:1.0 axi_adc]
|
||
|
|
set_property -dict [list \
|
||
|
|
CONFIG.NUM_CHANNELS 14 \
|
||
|
|
] $axi_adc
|
||
|
|
|
||
|
|
ad_connect processing/overflow axi_adc/adc_dovf
|
||
|
|
ad_connect axi_adc/adc_enable processing/channel_enable
|
||
|
|
|
||
|
|
connect_bd_net -net sys_cpu_clk \
|
||
|
|
[get_bd_pins /spi/clk] \
|
||
|
|
[get_bd_pins /processing/clk] \
|
||
|
|
[get_bd_pins /axi_dma/m_dest_axi_aclk] \
|
||
|
|
[get_bd_pins /axi_dma/fifo_wr_clk] \
|
||
|
|
[get_bd_pins /phase_gen/CLK] \
|
||
|
|
[get_bd_pins /axi_adc/adc_clk]
|
||
|
|
|
||
|
|
connect_bd_net -net sys_cpu_resetn \
|
||
|
|
[get_bd_pins /spi/resetn] \
|
||
|
|
[get_bd_pins /processing/resetn] \
|
||
|
|
[get_bd_pins /axi_dma/m_dest_axi_aresetn]
|
||
|
|
|
||
|
|
ad_connect /processing/dma_wr /axi_dma/fifo_wr
|
||
|
|
|
||
|
|
ad_cpu_interconnect 0x43c00000 /axi_adc
|
||
|
|
ad_cpu_interconnect 0x44a00000 /spi/axi
|
||
|
|
ad_cpu_interconnect 0x44a30000 /axi_dma
|
||
|
|
|
||
|
|
ad_cpu_interrupt "ps-13" "mb-13" /axi_dma/irq
|
||
|
|
ad_cpu_interrupt "ps-12" "mb-12" /spi/irq
|
||
|
|
|
||
|
|
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
|
||
|
|
ad_mem_hp2_interconnect sys_cpu_clk axi_dma/m_dest_axi
|