2014-09-01 15:34:31 +00:00
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# daq1
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2015-03-24 10:45:24 +00:00
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create_bd_port -dir I rx_ref_clk
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create_bd_port -dir O rx_sync
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create_bd_port -dir I rx_sysref
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create_bd_port -dir I -from 1 -to 0 rx_data_p
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create_bd_port -dir I -from 1 -to 0 rx_data_n
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create_bd_port -dir O dac_clk
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create_bd_port -dir O dac_valid_0
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create_bd_port -dir O dac_enable_0
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create_bd_port -dir I -from 63 -to 0 dac_ddata_0
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create_bd_port -dir O dac_valid_1
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create_bd_port -dir O dac_enable_1
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create_bd_port -dir I -from 63 -to 0 dac_ddata_1
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create_bd_port -dir I dac_drd
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create_bd_port -dir O -from 127 -to 0 dac_ddata
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create_bd_port -dir O adc_clk
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create_bd_port -dir O adc_enable_a
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create_bd_port -dir O adc_valid_a
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create_bd_port -dir O -from 31 -to 0 adc_data_a
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create_bd_port -dir O adc_enable_b
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create_bd_port -dir O adc_valid_b
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create_bd_port -dir O -from 31 -to 0 adc_data_b
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create_bd_port -dir I adc_dwr
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create_bd_port -dir I adc_dsync
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create_bd_port -dir I -from 63 -to 0 adc_ddata
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create_bd_port -dir I tx_ref_clk_p
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create_bd_port -dir I tx_ref_clk_n
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create_bd_port -dir O tx_clk_p
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create_bd_port -dir O tx_clk_n
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create_bd_port -dir O tx_frame_p
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create_bd_port -dir O tx_frame_n
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create_bd_port -dir O -from 15 -to 0 tx_data_p
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create_bd_port -dir O -from 15 -to 0 tx_data_n
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2014-11-24 16:08:34 +00:00
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2014-09-01 15:34:31 +00:00
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# dac peripherals
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2015-03-24 10:45:24 +00:00
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create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122_core
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create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] [get_bd_cells axi_ad9122_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] [get_bd_cells axi_ad9122_dma]
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set_property -dict [list CONFIG.PCORE_ID {1}] [get_bd_cells axi_ad9122_dma]
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] [get_bd_cells axi_ad9122_dma]
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] [get_bd_cells axi_ad9122_dma]
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] [get_bd_cells axi_ad9122_dma]
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] [get_bd_cells axi_ad9122_dma]
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set_property -dict [list CONFIG.C_CYCLIC {1}] [get_bd_cells axi_ad9122_dma]
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] [get_bd_cells axi_ad9122_dma]
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] [get_bd_cells axi_ad9122_dma]
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2014-09-01 15:34:31 +00:00
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# adc peripherals
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set axi_ad9250_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_core]
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2015-03-24 10:45:24 +00:00
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set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9250_jesd]
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2014-09-01 15:34:31 +00:00
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
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set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9250_jesd
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set axi_ad9250_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_dma
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# dac/adc common gt/gpio
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set axi_daq1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq1_gt]
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2014-11-24 16:16:14 +00:00
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set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {2}] $axi_daq1_gt
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set_property -dict [list CONFIG.PCORE_NUM_OF_TX_LANES {2}] $axi_daq1_gt
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2014-09-12 21:23:11 +00:00
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set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {2}] $axi_daq1_gt
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set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_daq1_gt
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set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_daq1_gt
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set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {10}] $axi_daq1_gt
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set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {10}] $axi_daq1_gt
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set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_daq1_gt
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set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_daq1_gt
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2014-09-01 15:34:31 +00:00
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# additions to default configuration
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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# connections (gt)
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2015-03-24 10:45:24 +00:00
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ad_connect rx_ref_clk axi_daq1_gt/ref_clk_c
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ad_connect rx_data_p axi_daq1_gt/rx_data_p
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ad_connect rx_data_n axi_daq1_gt/rx_data_n
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ad_connect rx_sync axi_daq1_gt/rx_sync
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ad_connect rx_sysref axi_daq1_gt/rx_ext_sysref
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ad_connect axi_daq1_gt/tx_clk axi_daq1_gt/tx_clk_g
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2014-09-01 15:34:31 +00:00
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# connections (adc)
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2014-09-23 18:23:19 +00:00
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2015-03-24 10:45:24 +00:00
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ad_connect axi_daq1_gt/rx_clk_g axi_daq1_gt/rx_clk
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ad_connect axi_daq1_gt/rx_clk_g axi_ad9250_core/rx_clk
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ad_connect axi_daq1_gt/rx_clk_g axi_ad9250_jesd/rx_core_clk
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set util_bsplit_rx_gt_charisk [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk]
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
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set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_charisk]
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ad_connect util_bsplit_rx_gt_charisk/data axi_daq1_gt/rx_gt_charisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9250_jesd/gt0_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad9250_jesd/gt1_rxcharisk
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set util_bsplit_gt_rxdisperr [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_gt_rxdisperr]
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_gt_rxdisperr]
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set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_gt_rxdisperr]
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ad_connect util_bsplit_gt_rxdisperr/data axi_daq1_gt/rx_gt_disperr
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ad_connect util_bsplit_gt_rxdisperr/split_data_0 axi_ad9250_jesd/gt0_rxdisperr
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ad_connect util_bsplit_gt_rxdisperr/split_data_1 axi_ad9250_jesd/gt1_rxdisperr
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set util_bsplit_rx_gt_notintable [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable]
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
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set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_notintable]
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ad_connect util_bsplit_rx_gt_notintable/data axi_daq1_gt/rx_gt_notintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9250_jesd/gt0_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad9250_jesd/gt1_rxnotintable
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set util_bsplit_rx_gt_data [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data]
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set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data]
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set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_data]
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ad_connect util_bsplit_rx_gt_data/data axi_daq1_gt/rx_gt_data
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ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9250_jesd/gt0_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad9250_jesd/gt1_rxdata
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2015-04-30 09:14:03 +00:00
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ad_connect axi_daq1_gt/rx_jesd_rst axi_ad9250_jesd/rx_reset
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2015-03-24 10:45:24 +00:00
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ad_connect axi_daq1_gt/rx_sysref axi_ad9250_jesd/rx_sysref
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ad_connect axi_daq1_gt/rx_rst_done axi_ad9250_jesd/rx_reset_done
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ad_connect axi_daq1_gt/rx_ip_comma_align axi_ad9250_jesd/rxencommaalign_out
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ad_connect axi_daq1_gt/rx_ip_sync axi_ad9250_jesd/rx_sync
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ad_connect axi_daq1_gt/rx_ip_sof axi_ad9250_jesd/rx_start_of_frame
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ad_connect axi_daq1_gt/rx_ip_data axi_ad9250_jesd/rx_tdata
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ad_connect axi_daq1_gt/rx_data axi_ad9250_core/rx_data
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ad_connect adc_clk axi_ad9250_core/adc_clk
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ad_connect axi_ad9250_core/adc_clk axi_ad9250_dma/fifo_wr_clk
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ad_connect adc_enable_a axi_ad9250_core/adc_enable_a
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ad_connect adc_valid_a axi_ad9250_core/adc_valid_a
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ad_connect adc_data_a axi_ad9250_core/adc_data_a
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ad_connect adc_enable_b axi_ad9250_core/adc_enable_b
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ad_connect adc_valid_b axi_ad9250_core/adc_valid_b
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ad_connect adc_data_b axi_ad9250_core/adc_data_b
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ad_connect axi_ad9250_core/adc_dovf axi_ad9250_dma/fifo_wr_overflow
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ad_connect adc_dwr axi_ad9250_dma/fifo_wr_en
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ad_connect adc_dsync axi_ad9250_dma/fifo_wr_sync
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ad_connect adc_ddata axi_ad9250_dma/fifo_wr_din
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2014-09-23 18:23:19 +00:00
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2014-09-01 15:34:31 +00:00
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# connections (dac)
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2015-03-24 10:45:24 +00:00
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ad_connect tx_ref_clk_p axi_ad9122_core/dac_clk_in_p
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ad_connect tx_ref_clk_n axi_ad9122_core/dac_clk_in_n
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ad_connect tx_clk_p axi_ad9122_core/dac_clk_out_p
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ad_connect tx_clk_n axi_ad9122_core/dac_clk_out_n
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ad_connect tx_frame_p axi_ad9122_core/dac_frame_out_p
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ad_connect tx_frame_n axi_ad9122_core/dac_frame_out_n
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ad_connect tx_data_p axi_ad9122_core/dac_data_out_p
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ad_connect tx_data_n axi_ad9122_core/dac_data_out_n
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ad_connect dac_clk axi_ad9122_core/dac_div_clk
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ad_connect axi_ad9122_core/dac_div_clk axi_ad9122_dma/fifo_rd_clk
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ad_connect dac_valid_0 axi_ad9122_core/dac_valid_0
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ad_connect dac_enable_0 axi_ad9122_core/dac_enable_0
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ad_connect dac_ddata_0 axi_ad9122_core/dac_ddata_0
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ad_connect dac_valid_1 axi_ad9122_core/dac_valid_1
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ad_connect dac_enable_1 axi_ad9122_core/dac_enable_1
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ad_connect dac_ddata_1 axi_ad9122_core/dac_ddata_1
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ad_connect dac_drd axi_ad9122_dma/fifo_rd_en
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ad_connect dac_ddata axi_ad9122_dma/fifo_rd_dout
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ad_connect axi_ad9122_core/dac_dunf axi_ad9122_dma/fifo_rd_underflow
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2014-09-23 18:23:19 +00:00
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2015-04-30 09:14:03 +00:00
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ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
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ad_connect sys_cpu_resetn axi_ad9250_dma/m_dest_axi_aresetn
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2014-09-01 15:34:31 +00:00
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# interconnect (cpu)
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2015-03-24 10:45:24 +00:00
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ad_cpu_interconnect 0x44A60000 axi_daq1_gt
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ad_cpu_interconnect 0x44A00000 axi_ad9122_core
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ad_cpu_interconnect 0x7c400000 axi_ad9122_dma
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ad_cpu_interconnect 0x44A10000 axi_ad9250_core
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ad_cpu_interconnect 0x7c420000 axi_ad9250_dma
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ad_cpu_interconnect 0x44A91000 axi_ad9250_jesd
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# memory interconnects
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ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi
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ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_dma/m_dest_axi
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk axi_daq1_gt/m_axi
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# interrupts
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ad_cpu_interrupt ps-13 mb-12 axi_ad9250_dma/irq
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ad_cpu_interrupt ps-12 mb-13 axi_ad9122_dma/irq
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2014-09-01 15:34:31 +00:00
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# ila
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2015-03-24 10:45:24 +00:00
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set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_jesd_rx_mon]
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2014-09-23 18:23:19 +00:00
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
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2015-06-09 08:50:27 +00:00
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {7} ] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {64} ] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {1} ] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_PROBE2_WIDTH {1} ] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_PROBE3_WIDTH {32} ] $ila_jesd_rx_mon
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2014-09-12 21:23:11 +00:00
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set_property -dict [list CONFIG.C_PROBE4_WIDTH {1} ] $ila_jesd_rx_mon
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2015-06-09 08:50:27 +00:00
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set_property -dict [list CONFIG.C_PROBE5_WIDTH {1} ] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_PROBE6_WIDTH {32} ] $ila_jesd_rx_mon
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2014-09-01 15:34:31 +00:00
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2015-03-24 10:45:24 +00:00
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ad_connect axi_daq1_gt/rx_clk_g ila_jesd_rx_mon/CLK
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2015-06-09 08:50:27 +00:00
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ad_connect axi_daq1_gt/rx_data ila_jesd_rx_mon/PROBE0
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ad_connect axi_ad9250_core/adc_valid_a ila_jesd_rx_mon/PROBE1
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ad_connect axi_ad9250_core/adc_enable_a ila_jesd_rx_mon/PROBE2
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ad_connect axi_ad9250_core/adc_data_a ila_jesd_rx_mon/PROBE3
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ad_connect axi_ad9250_core/adc_valid_b ila_jesd_rx_mon/PROBE4
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ad_connect axi_ad9250_core/adc_enable_a ila_jesd_rx_mon/PROBE5
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ad_connect axi_ad9250_core/adc_data_a ila_jesd_rx_mon/PROBE6
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2014-11-24 16:08:34 +00:00
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