406 lines
15 KiB
Plaintext
406 lines
15 KiB
Plaintext
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<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags="INTERNAL_COMPONENT=true"
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categories="" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element $${FILENAME}
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{
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}
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element jesd204_0
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
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<parameter name="device" value="10AX115S3F45I2SGE2" />
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<parameter name="deviceFamily" value="Arria 10" />
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<parameter name="deviceSpeedGrade" value="2" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="true" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="1" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface name="alldev_lane_aligned" internal="jesd204_0.alldev_lane_aligned" />
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<interface
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name="csr_bit_reversal"
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internal="jesd204_0.csr_bit_reversal"
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type="conduit"
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dir="end">
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<port name="csr_bit_reversal" internal="csr_bit_reversal" />
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</interface>
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<interface
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name="csr_byte_reversal"
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internal="jesd204_0.csr_byte_reversal"
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type="conduit"
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dir="end">
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<port name="csr_byte_reversal" internal="csr_byte_reversal" />
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</interface>
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<interface name="csr_cf" internal="jesd204_0.csr_cf" type="conduit" dir="end">
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<port name="csr_cf" internal="csr_cf" />
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</interface>
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<interface name="csr_cs" internal="jesd204_0.csr_cs" type="conduit" dir="end">
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<port name="csr_cs" internal="csr_cs" />
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</interface>
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<interface name="csr_f" internal="jesd204_0.csr_f" type="conduit" dir="end">
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<port name="csr_f" internal="csr_f" />
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</interface>
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<interface name="csr_hd" internal="jesd204_0.csr_hd" type="conduit" dir="end">
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<port name="csr_hd" internal="csr_hd" />
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</interface>
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<interface name="csr_k" internal="jesd204_0.csr_k" type="conduit" dir="end">
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<port name="csr_k" internal="csr_k" />
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</interface>
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<interface name="csr_l" internal="jesd204_0.csr_l" type="conduit" dir="end">
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<port name="csr_l" internal="csr_l" />
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</interface>
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<interface
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name="csr_lane_polarity"
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internal="jesd204_0.csr_lane_polarity"
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type="conduit"
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dir="end">
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<port name="csr_lane_polarity" internal="csr_lane_polarity" />
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</interface>
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<interface
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name="csr_lane_powerdown"
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internal="jesd204_0.csr_lane_powerdown"
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type="conduit"
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dir="end">
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<port name="csr_lane_powerdown" internal="csr_lane_powerdown" />
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</interface>
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<interface name="csr_m" internal="jesd204_0.csr_m" type="conduit" dir="end">
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<port name="csr_m" internal="csr_m" />
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</interface>
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<interface name="csr_n" internal="jesd204_0.csr_n" type="conduit" dir="end">
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<port name="csr_n" internal="csr_n" />
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</interface>
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<interface name="csr_np" internal="jesd204_0.csr_np" type="conduit" dir="end">
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<port name="csr_np" internal="csr_np" />
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</interface>
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<interface name="csr_rx_testmode" internal="jesd204_0.csr_rx_testmode" />
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<interface name="csr_s" internal="jesd204_0.csr_s" type="conduit" dir="end">
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<port name="csr_s" internal="csr_s" />
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</interface>
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<interface
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name="csr_tx_testmode"
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internal="jesd204_0.csr_tx_testmode"
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type="conduit"
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dir="end">
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<port name="csr_tx_testmode" internal="csr_tx_testmode" />
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</interface>
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<interface
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name="csr_tx_testpattern_a"
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internal="jesd204_0.csr_tx_testpattern_a"
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type="conduit"
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dir="end">
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<port name="csr_tx_testpattern_a" internal="csr_tx_testpattern_a" />
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</interface>
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<interface
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name="csr_tx_testpattern_b"
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internal="jesd204_0.csr_tx_testpattern_b"
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type="conduit"
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dir="end">
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<port name="csr_tx_testpattern_b" internal="csr_tx_testpattern_b" />
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</interface>
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<interface
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name="csr_tx_testpattern_c"
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internal="jesd204_0.csr_tx_testpattern_c"
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type="conduit"
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dir="end">
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<port name="csr_tx_testpattern_c" internal="csr_tx_testpattern_c" />
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</interface>
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<interface
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name="csr_tx_testpattern_d"
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internal="jesd204_0.csr_tx_testpattern_d"
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type="conduit"
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dir="end">
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<port name="csr_tx_testpattern_d" internal="csr_tx_testpattern_d" />
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</interface>
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<interface name="dev_lane_aligned" internal="jesd204_0.dev_lane_aligned" />
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<interface
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name="dev_sync_n"
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internal="jesd204_0.dev_sync_n"
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type="conduit"
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dir="end">
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<port name="dev_sync_n" internal="dev_sync_n" />
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</interface>
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<interface name="jesd204_rx_avs" internal="jesd204_0.jesd204_rx_avs" />
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<interface name="jesd204_rx_avs_clk" internal="jesd204_0.jesd204_rx_avs_clk" />
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<interface name="jesd204_rx_avs_rst_n" internal="jesd204_0.jesd204_rx_avs_rst_n" />
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<interface name="jesd204_rx_dlb_data" internal="jesd204_0.jesd204_rx_dlb_data" />
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<interface
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name="jesd204_rx_dlb_data_valid"
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internal="jesd204_0.jesd204_rx_dlb_data_valid" />
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<interface
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name="jesd204_rx_dlb_disperr"
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internal="jesd204_0.jesd204_rx_dlb_disperr" />
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<interface
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name="jesd204_rx_dlb_errdetect"
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internal="jesd204_0.jesd204_rx_dlb_errdetect" />
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<interface
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name="jesd204_rx_dlb_kchar_data"
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internal="jesd204_0.jesd204_rx_dlb_kchar_data" />
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<interface
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name="jesd204_rx_frame_error"
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internal="jesd204_0.jesd204_rx_frame_error" />
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<interface name="jesd204_rx_int" internal="jesd204_0.jesd204_rx_int" />
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<interface name="jesd204_rx_link" internal="jesd204_0.jesd204_rx_link" />
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<interface name="jesd204_rx_pcs_data" internal="jesd204_0.jesd204_rx_pcs_data" />
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<interface
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name="jesd204_rx_pcs_data_valid"
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internal="jesd204_0.jesd204_rx_pcs_data_valid" />
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<interface
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name="jesd204_rx_pcs_disperr"
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internal="jesd204_0.jesd204_rx_pcs_disperr" />
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<interface
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name="jesd204_rx_pcs_errdetect"
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internal="jesd204_0.jesd204_rx_pcs_errdetect" />
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<interface
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name="jesd204_rx_pcs_kchar_data"
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internal="jesd204_0.jesd204_rx_pcs_kchar_data" />
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<interface
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name="jesd204_tx_avs"
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internal="jesd204_0.jesd204_tx_avs"
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type="avalon"
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dir="end">
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<port name="jesd204_tx_avs_chipselect" internal="jesd204_tx_avs_chipselect" />
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<port name="jesd204_tx_avs_address" internal="jesd204_tx_avs_address" />
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<port name="jesd204_tx_avs_read" internal="jesd204_tx_avs_read" />
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<port name="jesd204_tx_avs_readdata" internal="jesd204_tx_avs_readdata" />
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<port
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name="jesd204_tx_avs_waitrequest"
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internal="jesd204_tx_avs_waitrequest" />
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<port name="jesd204_tx_avs_write" internal="jesd204_tx_avs_write" />
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<port name="jesd204_tx_avs_writedata" internal="jesd204_tx_avs_writedata" />
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</interface>
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<interface
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name="jesd204_tx_avs_clk"
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internal="jesd204_0.jesd204_tx_avs_clk"
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type="clock"
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dir="end">
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<port name="jesd204_tx_avs_clk" internal="jesd204_tx_avs_clk" />
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</interface>
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<interface
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name="jesd204_tx_avs_rst_n"
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internal="jesd204_0.jesd204_tx_avs_rst_n"
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type="reset"
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dir="end">
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<port name="jesd204_tx_avs_rst_n" internal="jesd204_tx_avs_rst_n" />
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</interface>
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<interface
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name="jesd204_tx_frame_error"
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internal="jesd204_0.jesd204_tx_frame_error"
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type="conduit"
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dir="end">
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<port name="jesd204_tx_frame_error" internal="jesd204_tx_frame_error" />
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</interface>
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<interface
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name="jesd204_tx_frame_ready"
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internal="jesd204_0.jesd204_tx_frame_ready"
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type="conduit"
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dir="end">
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<port name="jesd204_tx_frame_ready" internal="jesd204_tx_frame_ready" />
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</interface>
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<interface
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name="jesd204_tx_int"
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internal="jesd204_0.jesd204_tx_int"
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type="interrupt"
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dir="end">
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<port name="jesd204_tx_int" internal="jesd204_tx_int" />
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</interface>
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<interface
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name="jesd204_tx_link"
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internal="jesd204_0.jesd204_tx_link"
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type="avalon_streaming"
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dir="end">
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<port name="jesd204_tx_link_data" internal="jesd204_tx_link_data" />
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<port name="jesd204_tx_link_valid" internal="jesd204_tx_link_valid" />
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<port name="jesd204_tx_link_ready" internal="jesd204_tx_link_ready" />
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</interface>
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<interface
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name="jesd204_tx_pcs_data"
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internal="jesd204_0.jesd204_tx_pcs_data"
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type="conduit"
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dir="end">
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<port name="jesd204_tx_pcs_data" internal="jesd204_tx_pcs_data" />
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</interface>
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<interface
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name="jesd204_tx_pcs_kchar_data"
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internal="jesd204_0.jesd204_tx_pcs_kchar_data"
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type="conduit"
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dir="end">
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<port name="jesd204_tx_pcs_kchar_data" internal="jesd204_tx_pcs_kchar_data" />
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</interface>
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<interface
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name="mdev_sync_n"
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internal="jesd204_0.mdev_sync_n"
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type="conduit"
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dir="end">
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<port name="mdev_sync_n" internal="mdev_sync_n" />
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</interface>
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<interface name="patternalign_en" internal="jesd204_0.patternalign_en" />
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<interface
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name="phy_csr_rx_pcfifo_empty"
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internal="jesd204_0.phy_csr_rx_pcfifo_empty" />
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<interface
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name="phy_csr_rx_pcfifo_full"
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internal="jesd204_0.phy_csr_rx_pcfifo_full" />
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<interface
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name="phy_csr_tx_pcfifo_empty"
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internal="jesd204_0.phy_csr_tx_pcfifo_empty"
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type="conduit"
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dir="end">
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<port name="phy_csr_tx_pcfifo_empty" internal="phy_csr_tx_pcfifo_empty" />
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</interface>
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<interface
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name="phy_csr_tx_pcfifo_full"
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internal="jesd204_0.phy_csr_tx_pcfifo_full"
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type="conduit"
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dir="end">
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<port name="phy_csr_tx_pcfifo_full" internal="phy_csr_tx_pcfifo_full" />
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</interface>
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<interface
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name="phy_tx_elecidle"
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internal="jesd204_0.phy_tx_elecidle"
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type="conduit"
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dir="end">
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<port name="phy_tx_elecidle" internal="phy_tx_elecidle" />
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</interface>
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<interface
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name="pll_locked"
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internal="jesd204_0.pll_locked"
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type="conduit"
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dir="end">
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<port name="pll_locked" internal="pll_locked" />
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</interface>
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<interface name="pll_ref_clk" internal="jesd204_0.pll_ref_clk" />
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<interface name="rx_analogreset" internal="jesd204_0.rx_analogreset" />
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<interface name="rx_cal_busy" internal="jesd204_0.rx_cal_busy" />
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<interface name="rx_digitalreset" internal="jesd204_0.rx_digitalreset" />
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<interface name="rx_islockedtodata" internal="jesd204_0.rx_islockedtodata" />
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<interface name="rx_serial_data" internal="jesd204_0.rx_serial_data" />
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<interface name="rxlink_clk" internal="jesd204_0.rxlink_clk" />
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<interface name="rxlink_rst_n" internal="jesd204_0.rxlink_rst_n" />
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<interface name="rxphy_clk" internal="jesd204_0.rxphy_clk" />
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<interface name="sof" internal="jesd204_0.sof" />
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<interface name="somf" internal="jesd204_0.somf" />
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<interface name="sync_n" internal="jesd204_0.sync_n" type="conduit" dir="end">
|
||
|
|
<port name="sync_n" internal="sync_n" />
|
||
|
|
</interface>
|
||
|
|
<interface name="sysref" internal="jesd204_0.sysref" type="conduit" dir="end">
|
||
|
|
<port name="sysref" internal="sysref" />
|
||
|
|
</interface>
|
||
|
|
<interface name="tx_analogreset" internal="jesd204_0.tx_analogreset" />
|
||
|
|
<interface name="tx_bonding_clocks" internal="jesd204_0.tx_bonding_clocks" />
|
||
|
|
<interface
|
||
|
|
name="tx_cal_busy"
|
||
|
|
internal="jesd204_0.tx_cal_busy"
|
||
|
|
type="conduit"
|
||
|
|
dir="end">
|
||
|
|
<port name="tx_cal_busy" internal="tx_cal_busy" />
|
||
|
|
</interface>
|
||
|
|
<interface name="tx_digitalreset" internal="jesd204_0.tx_digitalreset" />
|
||
|
|
<interface name="tx_serial_clk0" internal="jesd204_0.tx_serial_clk0" />
|
||
|
|
<interface name="tx_serial_data" internal="jesd204_0.tx_serial_data" />
|
||
|
|
<interface
|
||
|
|
name="txlink_clk"
|
||
|
|
internal="jesd204_0.txlink_clk"
|
||
|
|
type="clock"
|
||
|
|
dir="end">
|
||
|
|
<port name="txlink_clk" internal="txlink_clk" />
|
||
|
|
</interface>
|
||
|
|
<interface
|
||
|
|
name="txlink_rst_n"
|
||
|
|
internal="jesd204_0.txlink_rst_n"
|
||
|
|
type="reset"
|
||
|
|
dir="end">
|
||
|
|
<port name="txlink_rst_n_reset_n" internal="txlink_rst_n_reset_n" />
|
||
|
|
</interface>
|
||
|
|
<interface name="txphy_clk" internal="jesd204_0.txphy_clk" />
|
||
|
|
<module
|
||
|
|
name="jesd204_0"
|
||
|
|
kind="altera_jesd204"
|
||
|
|
version="15.0"
|
||
|
|
enabled="1"
|
||
|
|
autoexport="1">
|
||
|
|
<parameter name="ADJCNT" value="0" />
|
||
|
|
<parameter name="ADJDIR" value="0" />
|
||
|
|
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
|
||
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||
|
|
<parameter name="BID" value="0" />
|
||
|
|
<parameter name="CF" value="0" />
|
||
|
|
<parameter name="CS" value="0" />
|
||
|
|
<parameter name="DATA_PATH" value="TX" />
|
||
|
|
<parameter name="DEVICE_FAMILY" value="Arria 10" />
|
||
|
|
<parameter name="DID" value="0" />
|
||
|
|
<parameter name="DLB_TEST" value="0" />
|
||
|
|
<parameter name="ECC_EN" value="0" />
|
||
|
|
<parameter name="GUI_CFG_F" value="1" />
|
||
|
|
<parameter name="GUI_EN_CFG_F" value="true" />
|
||
|
|
<parameter name="HD" value="1" />
|
||
|
|
<parameter name="JESDV" value="1" />
|
||
|
|
<parameter name="K" value="32" />
|
||
|
|
<parameter name="L" value="4" />
|
||
|
|
<parameter name="LID0" value="0" />
|
||
|
|
<parameter name="LID1" value="1" />
|
||
|
|
<parameter name="LID2" value="2" />
|
||
|
|
<parameter name="LID3" value="3" />
|
||
|
|
<parameter name="LID4" value="4" />
|
||
|
|
<parameter name="LID5" value="5" />
|
||
|
|
<parameter name="LID6" value="6" />
|
||
|
|
<parameter name="LID7" value="7" />
|
||
|
|
<parameter name="M" value="2" />
|
||
|
|
<parameter name="N" value="16" />
|
||
|
|
<parameter name="N_PRIME" value="16" />
|
||
|
|
<parameter name="OPTIMIZE" value="0" />
|
||
|
|
<parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
|
||
|
|
<parameter name="PHADJ" value="0" />
|
||
|
|
<parameter name="REFCLK_FREQ" value="125.0" />
|
||
|
|
<parameter name="RES1" value="0" />
|
||
|
|
<parameter name="RES2" value="0" />
|
||
|
|
<parameter name="S" value="1" />
|
||
|
|
<parameter name="SCR" value="1" />
|
||
|
|
<parameter name="SUBCLASSV" value="1" />
|
||
|
|
<parameter name="TERMINATE_RECONFIG_EN" value="false" />
|
||
|
|
<parameter name="TEST_COMPONENTS_EN" value="false" />
|
||
|
|
<parameter name="bitrev_en" value="false" />
|
||
|
|
<parameter name="bonded_mode" value="non_bonded" />
|
||
|
|
<parameter name="lane_rate" value="10000.0" />
|
||
|
|
<parameter name="part_trait_bd" value="NIGHTFURY5ES2" />
|
||
|
|
<parameter name="part_trait_dp" value="10AX115S3F45I2SGE2" />
|
||
|
|
<parameter name="pll_reconfig_enable" value="false" />
|
||
|
|
<parameter name="pll_type" value="CMU" />
|
||
|
|
<parameter name="rcfg_jtag_enable" value="false" />
|
||
|
|
<parameter name="sdc_constraint" value="1.0" />
|
||
|
|
<parameter name="set_capability_reg_enable" value="false" />
|
||
|
|
<parameter name="set_csr_soft_logic_enable" value="false" />
|
||
|
|
<parameter name="set_prbs_soft_logic_enable" value="false" />
|
||
|
|
<parameter name="set_user_identifier" value="0" />
|
||
|
|
<parameter name="wrapper_opt" value="base" />
|
||
|
|
</module>
|
||
|
|
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||
|
|
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
|
||
|
|
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||
|
|
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||
|
|
</system>
|