2022-01-31 12:18:12 +00:00
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 cn0561_di
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create_bd_port -dir O cn0561_odr
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create_bd_cell -type hier cn0561_spi
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current_bd_instance /cn0561_spi
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type clk spi_clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I odr
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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if {$adc_resolution == 16 || $adc_resolution == 24} {
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set data_width 32
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} elseif {$adc_resolution == 32} {
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set data_width 64
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};
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ad_ip_instance spi_engine_execution execution
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ad_ip_parameter execution CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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ad_ip_parameter execution CONFIG.NUM_OF_SDI $adc_num_of_channels
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ad_ip_instance axi_spi_engine axi
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ad_ip_parameter axi CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter axi CONFIG.NUM_OF_SDI $adc_num_of_channels
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ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
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ad_ip_parameter axi CONFIG.ASYNC_SPI_CLK 1
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ad_ip_instance spi_engine_offload offload
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ad_ip_parameter offload CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter offload CONFIG.NUM_OF_SDI $adc_num_of_channels
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ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
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ad_ip_parameter offload CONFIG.ASYNC_SPI_CLK 1
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter interconnect CONFIG.NUM_OF_SDI $adc_num_of_channels
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ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi M_AXIS_SAMPLE
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ad_connect execution/spi m_spi
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ad_connect spi_clk offload/spi_clk
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ad_connect spi_clk offload/ctrl_clk
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ad_connect spi_clk execution/clk
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ad_connect clk axi/s_axi_aclk
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ad_connect spi_clk axi/spi_clk
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ad_connect spi_clk interconnect/clk
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ad_connect axi/spi_resetn offload/spi_resetn
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ad_connect axi/spi_resetn execution/resetn
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ad_connect axi/spi_resetn interconnect/resetn
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ad_connect odr offload/trigger
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ad_connect resetn axi/s_axi_aresetn
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ad_connect irq axi/irq
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current_bd_instance /
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# clkgen
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ad_ip_instance axi_clkgen axi_cn0561_clkgen
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ad_ip_parameter axi_cn0561_clkgen CONFIG.VCO_DIV 5
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ad_ip_parameter axi_cn0561_clkgen CONFIG.VCO_MUL 48
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ad_ip_parameter axi_cn0561_clkgen CONFIG.CLK0_DIV 10
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# dma to receive data stream
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ad_ip_instance axi_dmac axi_cn0561_dma
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ad_ip_parameter axi_cn0561_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_cn0561_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_cn0561_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_cn0561_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_cn0561_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_cn0561_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $adc_num_of_channels]
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ad_ip_parameter axi_cn0561_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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# odr generator
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ad_ip_instance axi_pwm_gen odr_generator
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ad_ip_parameter odr_generator CONFIG.N_PWMS 1
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ad_ip_parameter odr_generator CONFIG.PULSE_0_PERIOD 10000
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ad_ip_parameter odr_generator CONFIG.PULSE_0_WIDTH 4
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ad_ip_parameter odr_generator CONFIG.ASYNC_CLK_EN 0
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create_bd_cell -type module -reference sync_bits busy_sync
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create_bd_cell -type module -reference ad_edge_detect busy_capture
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set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture]
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ad_connect odr_generator/pwm_0 cn0561_odr
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ad_connect axi_cn0561_clkgen/clk_0 busy_capture/clk
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ad_connect axi_cn0561_clkgen/clk_0 busy_sync/out_clk
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ad_connect busy_capture/rst GND
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ad_connect cn0561_spi/axi/spi_resetn busy_sync/out_resetn
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ad_connect cn0561_odr busy_sync/in_bits
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ad_connect busy_sync/out_bits busy_capture/signal_in
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ad_connect busy_capture/signal_out cn0561_spi/odr
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ad_connect axi_cn0561_clkgen/clk_0 cn0561_spi/spi_clk
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ad_connect sys_cpu_clk axi_cn0561_clkgen/clk
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ad_connect sys_cpu_clk cn0561_spi/clk
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ad_connect axi_cn0561_clkgen/clk_0 axi_cn0561_dma/s_axis_aclk
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ad_connect sys_cpu_resetn cn0561_spi/resetn
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ad_connect sys_cpu_resetn axi_cn0561_dma/m_dest_axi_aresetn
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ad_connect cn0561_spi/m_spi cn0561_di
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ad_connect axi_cn0561_dma/s_axis cn0561_spi/M_AXIS_SAMPLE
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ad_cpu_interconnect 0x44a00000 cn0561_spi/axi
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ad_cpu_interconnect 0x44a30000 axi_cn0561_dma
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ad_cpu_interconnect 0x44b00000 odr_generator
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ad_cpu_interconnect 0x44b10000 axi_cn0561_clkgen
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ad_cpu_interrupt "ps-13" "mb-13" axi_cn0561_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" cn0561_spi/irq
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2022-09-29 12:14:57 +00:00
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ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_cpu_clk axi_cn0561_dma/m_dest_axi
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2022-01-31 12:18:12 +00:00
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