2015-05-11 14:17:07 +00:00
|
|
|
|
2015-06-01 14:59:33 +00:00
|
|
|
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
|
2017-08-17 11:15:40 +00:00
|
|
|
create_clock -period "3.000 ns" -name rx_ref_clk [get_ports {rx_ref_clk}]
|
|
|
|
|
create_clock -period "3.000 ns" -name tx_ref_clk [get_ports {tx_ref_clk}]
|
2015-05-11 14:17:07 +00:00
|
|
|
|
|
|
|
|
derive_pll_clocks
|
2015-07-13 14:07:18 +00:00
|
|
|
derive_clock_uncertainty
|
2015-05-11 14:17:07 +00:00
|
|
|
|
2017-06-06 20:09:15 +00:00
|
|
|
set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
|
2017-07-20 02:41:37 +00:00
|
|
|
|
|
|
|
|
set_false_path -from * -to [get_ports {flash_resetn}]
|
|
|
|
|
|
