2015-05-11 14:17:07 +00:00
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2015-06-01 14:59:33 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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2017-08-17 11:15:40 +00:00
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create_clock -period "3.000 ns" -name rx_ref_clk [get_ports {rx_ref_clk}]
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create_clock -period "3.000 ns" -name tx_ref_clk [get_ports {tx_ref_clk}]
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2015-05-11 14:17:07 +00:00
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derive_pll_clocks
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2015-07-13 14:07:18 +00:00
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derive_clock_uncertainty
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2015-05-11 14:17:07 +00:00
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2017-06-06 20:09:15 +00:00
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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2017-07-20 02:41:37 +00:00
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# flash interface
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_addr[*]} ]
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set_input_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ]
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ]
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_cen[*]} ]
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_oen} ]
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_resetn} ]
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_wen} ]
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set_false_path -from * -to [get_ports {flash_resetn}]
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