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axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
// ***************************************************************************
// ***************************************************************************
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
//
license: Add some clarification to the header license
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// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
//
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
//
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
// 1. The GNU General Public License version 2 as published by the
license: Add some clarification to the header license
2017-05-31 15:15:24 +00:00
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
//
// OR
//
license: Add some clarification to the header license
2017-05-31 15:15:24 +00:00
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
all: Update verilog files to verilog-2001
2017-04-13 08:45:54 +00:00
module up_tdd_cntrl #(
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
all: Update verilog files to verilog-2001
2017-04-13 08:45:54 +00:00
parameter ID = 0) (
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
all: Update verilog files to verilog-2001
2017-04-13 08:45:54 +00:00
input clk,
input rst,
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
all: Update verilog files to verilog-2001
2017-04-13 08:45:54 +00:00
//rf tdd interface control
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
all: Update verilog files to verilog-2001
2017-04-13 08:45:54 +00:00
output tdd_enable,
output tdd_secondary,
output tdd_rx_only,
output tdd_tx_only,
output tdd_gated_rx_dmapath,
output tdd_gated_tx_dmapath,
output [ 7:0] tdd_burst_count,
output [23:0] tdd_counter_init,
output [23:0] tdd_frame_length,
output tdd_terminal_type,
output [23:0] tdd_vco_rx_on_1,
output [23:0] tdd_vco_rx_off_1,
output [23:0] tdd_vco_tx_on_1,
output [23:0] tdd_vco_tx_off_1,
output [23:0] tdd_rx_on_1,
output [23:0] tdd_rx_off_1,
output [23:0] tdd_rx_dp_on_1,
output [23:0] tdd_rx_dp_off_1,
output [23:0] tdd_tx_on_1,
output [23:0] tdd_tx_off_1,
output [23:0] tdd_tx_dp_on_1,
output [23:0] tdd_tx_dp_off_1,
output [23:0] tdd_vco_rx_on_2,
output [23:0] tdd_vco_rx_off_2,
output [23:0] tdd_vco_tx_on_2,
output [23:0] tdd_vco_tx_off_2,
output [23:0] tdd_rx_on_2,
output [23:0] tdd_rx_off_2,
output [23:0] tdd_rx_dp_on_2,
output [23:0] tdd_rx_dp_off_2,
output [23:0] tdd_tx_on_2,
output [23:0] tdd_tx_off_2,
output [23:0] tdd_tx_dp_on_2,
output [23:0] tdd_tx_dp_off_2,
input [ 7:0] tdd_status,
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
// bus interface
all: Update verilog files to verilog-2001
2017-04-13 08:45:54 +00:00
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
up_tdd_cntrl: Set PCORE version to 1.00.a
2016-09-21 07:27:28 +00:00
localparam PCORE_VERSION = 32'h00010061;
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
// internal registers
reg [31:0] up_scratch = 32'h0;
reg up_tdd_enable = 1'h0;
reg up_tdd_secondary = 1'h0;
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
reg up_tdd_rx_only = 1'h0;
reg up_tdd_tx_only = 1'h0;
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
reg up_tdd_gated_tx_dmapath = 1'h0;
reg up_tdd_gated_rx_dmapath = 1'h0;
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
reg up_tdd_terminal_type = 1'h0;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
reg [ 7:0] up_tdd_burst_count = 8'h0;
reg [23:0] up_tdd_counter_init = 24'h0;
reg [23:0] up_tdd_frame_length = 24'h0;
reg [23:0] up_tdd_vco_rx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_1 = 24'h0;
reg [23:0] up_tdd_rx_on_1 = 24'h0;
reg [23:0] up_tdd_rx_off_1 = 24'h0;
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
reg [23:0] up_tdd_rx_dp_on_1 = 24'h0;
reg [23:0] up_tdd_rx_dp_off_1 = 24'h0;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
reg [23:0] up_tdd_tx_on_1 = 24'h0;
reg [23:0] up_tdd_tx_off_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_2 = 24'h0;
reg [23:0] up_tdd_rx_on_2 = 24'h0;
reg [23:0] up_tdd_rx_off_2 = 24'h0;
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
reg [23:0] up_tdd_rx_dp_on_2 = 24'h0;
reg [23:0] up_tdd_rx_dp_off_2 = 24'h0;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
reg [23:0] up_tdd_tx_on_2 = 24'h0;
reg [23:0] up_tdd_tx_off_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_2 = 24'h0;
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [ 7:0] up_tdd_status_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h20) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h20) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 1'h0;
up_scratch <= 32'h0;
up_tdd_enable <= 1'h0;
up_tdd_secondary <= 1'h0;
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
up_tdd_rx_only <= 1'h0;
up_tdd_tx_only <= 1'h0;
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
up_tdd_gated_tx_dmapath <= 1'h0;
up_tdd_gated_rx_dmapath <= 1'h0;
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
up_tdd_terminal_type <= 1'h0;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_counter_init <= 24'h0;
up_tdd_frame_length <= 24'h0;
up_tdd_burst_count <= 8'h0;
up_tdd_vco_rx_on_1 <= 24'h0;
up_tdd_vco_rx_off_1 <= 24'h0;
up_tdd_vco_tx_on_1 <= 24'h0;
up_tdd_vco_tx_off_1 <= 24'h0;
up_tdd_rx_on_1 <= 24'h0;
up_tdd_rx_off_1 <= 24'h0;
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
up_tdd_rx_dp_on_1 <= 24'h0;
up_tdd_rx_dp_off_1 <= 24'h0;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_on_1 <= 24'h0;
up_tdd_tx_off_1 <= 24'h0;
up_tdd_tx_dp_on_1 <= 24'h0;
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
up_tdd_tx_dp_off_1 <= 24'h0;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_rx_on_2 <= 24'h0;
up_tdd_vco_rx_off_2 <= 24'h0;
up_tdd_vco_tx_on_2 <= 24'h0;
up_tdd_vco_tx_off_2 <= 24'h0;
up_tdd_rx_on_2 <= 24'h0;
up_tdd_rx_off_2 <= 24'h0;
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
up_tdd_rx_dp_on_2 <= 24'h0;
up_tdd_rx_dp_off_2 <= 24'h0;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_on_2 <= 24'h0;
up_tdd_tx_off_2 <= 24'h0;
up_tdd_tx_dp_on_2 <= 24'h0;
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
up_tdd_tx_dp_off_2 <= 24'h0;
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end else begin
up_wack <= up_wreq_s;
library/tdd_control: Add common registers to the register map and fix init value of a register + Software in general needs to have access to the VERSION register. + tdd_sync_d3 registers init value should be 1'b0
2015-10-16 08:55:22 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_enable <= up_wdata[0];
up_tdd_secondary <= up_wdata[1];
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
up_tdd_rx_only <= up_wdata[2];
up_tdd_tx_only <= up_wdata[3];
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
up_tdd_gated_rx_dmapath <= up_wdata[4];
up_tdd_gated_tx_dmapath <= up_wdata[5];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
axi_ad9361&TDD: Update TDD + Delete unnecessary registers + Add the module ad_addsub.v to resolve additions and subtractions inside TDD control + Redefine the burst logic + Redesign the control signal generations + Note: This patch fix the TDD related timing violations
2015-05-13 11:03:01 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_burst_count <= up_wdata[7:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_counter_init <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_frame_length <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
util_tdd_sync: Update the synchronization interface Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-10 10:43:16 +00:00
up_tdd_terminal_type <= up_wdata[0];
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
end
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_rx_on_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_rx_off_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_tx_on_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_tx_off_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_rx_on_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h25)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_rx_off_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h26)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_on_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h27)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_off_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
up_tdd_rx_dp_on_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
up_tdd_rx_dp_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2a)) begin
up_tdd_tx_dp_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2b)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_dp_off_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_rx_on_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h31)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_rx_off_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_tx_on_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_tx_off_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h34)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_rx_on_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h35)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_rx_off_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h36)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_on_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
up_tdd_cntrl: Fix memory map register writes
2016-11-01 08:06:57 +00:00
up_tdd_tx_off_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
up_tdd_rx_dp_on_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin
up_tdd_cntrl: Fix memory map register writes
2016-11-01 08:06:57 +00:00
up_tdd_rx_dp_off_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3a)) begin
up_tdd_tx_dp_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3b)) begin
up_tdd_tx_dp_off_2 <= up_wdata[23:0];
end
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 1'b0;
up_rdata <= 1'b0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
library/tdd_control: Add common registers to the register map and fix init value of a register + Software in general needs to have access to the VERSION register. + tdd_sync_d3 registers init value should be 1'b0
2015-10-16 08:55:22 +00:00
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
8'h10: up_rdata <= {28'h0, up_tdd_gated_tx_dmapath,
up_tdd_gated_rx_dmapath,
up_tdd_tx_only,
up_tdd_rx_only,
up_tdd_secondary,
up_tdd_enable};
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
8'h12: up_rdata <= { 8'h0, up_tdd_counter_init};
8'h13: up_rdata <= { 8'h0, up_tdd_frame_length};
util_tdd_sync: Update the synchronization interface Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-10 10:43:16 +00:00
8'h14: up_rdata <= {31'h0, up_tdd_terminal_type};
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
8'h18: up_rdata <= {24'h0, up_tdd_status_s};
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1};
8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1};
8'h22: up_rdata <= { 8'h0, up_tdd_vco_tx_on_1};
8'h23: up_rdata <= { 8'h0, up_tdd_vco_tx_off_1};
8'h24: up_rdata <= { 8'h0, up_tdd_rx_on_1};
8'h25: up_rdata <= { 8'h0, up_tdd_rx_off_1};
8'h26: up_rdata <= { 8'h0, up_tdd_tx_on_1};
8'h27: up_rdata <= { 8'h0, up_tdd_tx_off_1};
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
8'h28: up_rdata <= { 8'h0, up_tdd_rx_dp_on_1};
8'h29: up_rdata <= { 8'h0, up_tdd_rx_dp_off_1};
8'h2a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1};
8'h2b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1};
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
8'h30: up_rdata <= { 8'h0, up_tdd_vco_rx_on_2};
8'h31: up_rdata <= { 8'h0, up_tdd_vco_rx_off_2};
8'h32: up_rdata <= { 8'h0, up_tdd_vco_tx_on_2};
8'h33: up_rdata <= { 8'h0, up_tdd_vco_tx_off_2};
8'h34: up_rdata <= { 8'h0, up_tdd_rx_on_2};
8'h35: up_rdata <= { 8'h0, up_tdd_rx_off_2};
8'h36: up_rdata <= { 8'h0, up_tdd_tx_on_2};
8'h37: up_rdata <= { 8'h0, up_tdd_tx_off_2};
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
8'h38: up_rdata <= { 8'h0, up_tdd_rx_dp_on_2};
8'h39: up_rdata <= { 8'h0, up_tdd_rx_dp_off_2};
8'h3a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2};
8'h3b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2};
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
default: up_rdata <= 32'h0;
endcase
end
end
end
// rf tdd control signal CDC
util_tdd_sync: Update the synchronization interface Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-10 10:43:16 +00:00
up_xfer_cntrl #(.DATA_WIDTH(15)) i_xfer_tdd_control (
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_enable,
up_tdd_secondary,
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
up_tdd_rx_only,
up_tdd_tx_only,
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
up_tdd_gated_rx_dmapath,
up_tdd_gated_tx_dmapath,
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
up_tdd_burst_count,
util_tdd_sync: Update the synchronization interface Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-10 10:43:16 +00:00
up_tdd_terminal_type
}),
ad9361/tdd: Fix generation of tx_valid_* signals In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals. In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 13:21:40 +00:00
.up_xfer_done(),
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
.d_rst(rst),
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
.d_clk(clk),
.d_data_cntrl({tdd_enable,
tdd_secondary,
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
tdd_rx_only,
tdd_tx_only,
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
tdd_gated_rx_dmapath,
tdd_gated_tx_dmapath,
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
tdd_burst_count,
util_tdd_sync: Update the synchronization interface Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-10 10:43:16 +00:00
tdd_terminal_type
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
}));
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
up_xfer_cntrl #(.DATA_WIDTH(624)) i_xfer_tdd_counter_values (
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_counter_init,
up_tdd_frame_length,
up_tdd_vco_rx_on_1,
up_tdd_vco_rx_off_1,
up_tdd_vco_tx_on_1,
up_tdd_vco_tx_off_1,
up_tdd_rx_on_1,
up_tdd_rx_off_1,
up_tdd_tx_on_1,
up_tdd_tx_off_1,
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
up_tdd_rx_dp_on_1,
up_tdd_rx_dp_off_1,
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
up_tdd_tx_dp_on_1,
up_tdd_tx_dp_off_1,
up_tdd_vco_rx_on_2,
up_tdd_vco_rx_off_2,
up_tdd_vco_tx_on_2,
up_tdd_vco_tx_off_2,
up_tdd_rx_on_2,
up_tdd_rx_off_2,
up_tdd_tx_on_2,
up_tdd_tx_off_2,
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
up_tdd_rx_dp_on_2,
up_tdd_rx_dp_off_2,
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
up_tdd_tx_dp_on_2,
up_tdd_tx_dp_off_2
}),
.up_xfer_done(),
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
.d_rst(rst),
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
.d_clk(clk),
.d_data_cntrl({tdd_counter_init,
tdd_frame_length,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
tdd_rx_dp_on_1,
tdd_rx_dp_off_1,
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
ad_tdd_control: Add an on/off switch to the receive datapath For a more robust control, add an on/off switch to the receive datapath too, in order to filter out transition noises.
2016-07-28 10:29:09 +00:00
tdd_rx_dp_on_2,
tdd_rx_dp_off_2,
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
tdd_tx_dp_on_2,
tdd_tx_dp_off_2
}));
axi_ad9361: Delete the old sync generator from the core + Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type + Delete to old ad_tdd_sync.v instances from the core + Update Make files + Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain) + Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle + Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 09:06:19 +00:00
up_xfer_status #(.DATA_WIDTH(8)) i_xfer_tdd_status (
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status (up_tdd_status_s),
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
.d_rst (rst),
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
.d_clk (clk),
.d_data_status (tdd_status));
endmodule
// ***************************************************************************
// ***************************************************************************