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pluto_hdl_adi/projects/daq2/zc706/system_bd.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
axi_adc/dacfifo: Split the intergration script file Split the integration script file into two separate script files. Rename the integration processes names to be more meaningful.
2016-05-05 06:40:25 +00:00
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
dmafifo- adc/dac split
2016-08-16 16:54:29 +00:00
source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
axi_adc/dacfifo: Split the intergration script file Split the integration script file into two separate script files. Rename the integration processes names to be more meaningful.
2016-05-05 06:40:25 +00:00
p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9680_fifo/sys_rst
ad_connect sys_clk axi_ad9680_fifo/sys_clk
ad_connect ddr3 axi_ad9680_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/daq2_bd.tcl