2015-06-26 09:04:19 +00:00
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// ***************************************************************************
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// ***************************************************************************
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2017-05-17 08:44:52 +00:00
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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2015-06-26 09:04:19 +00:00
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//
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2017-05-17 08:44:52 +00:00
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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2015-06-26 09:04:19 +00:00
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//
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2017-05-17 08:44:52 +00:00
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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2015-06-26 09:04:19 +00:00
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//
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2017-05-17 08:44:52 +00:00
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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2015-06-26 09:04:19 +00:00
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//
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// ***************************************************************************
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// ***************************************************************************
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// black box definition for pr module
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`timescale 1ns/100ps
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2015-10-13 08:36:45 +00:00
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(* black_box *)
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2015-06-26 09:04:19 +00:00
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module prcfg (
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2015-10-13 08:36:45 +00:00
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input clk,
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input [31:0] adc_gpio_input,
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output [31:0] adc_gpio_output,
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input [31:0] dac_gpio_input,
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output [31:0] dac_gpio_output,
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input dma_dac_i0_enable,
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output [15:0] dma_dac_i0_data,
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input dma_dac_i0_valid,
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input dma_dac_q0_enable,
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output [15:0] dma_dac_q0_data,
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input dma_dac_q0_valid,
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input dma_dac_i1_enable,
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output [15:0] dma_dac_i1_data,
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input dma_dac_i1_valid,
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input dma_dac_q1_enable,
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output [15:0] dma_dac_q1_data,
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input dma_dac_q1_valid,
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output core_dac_i0_enable,
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input [15:0] core_dac_i0_data,
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output core_dac_i0_valid,
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output core_dac_q0_enable,
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input [15:0] core_dac_q0_data,
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output core_dac_q0_valid,
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output core_dac_i1_enable,
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input [15:0] core_dac_i1_data,
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output core_dac_i1_valid,
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output core_dac_q1_enable,
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input [15:0] core_dac_q1_data,
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output core_dac_q1_valid,
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input dma_adc_i0_enable,
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input [15:0] dma_adc_i0_data,
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input dma_adc_i0_valid,
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input dma_adc_q0_enable,
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input [15:0] dma_adc_q0_data,
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input dma_adc_q0_valid,
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input dma_adc_i1_enable,
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input [15:0] dma_adc_i1_data,
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input dma_adc_i1_valid,
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input dma_adc_q1_enable,
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input [15:0] dma_adc_q1_data,
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input dma_adc_q1_valid,
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output core_adc_i0_enable,
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output [15:0] core_adc_i0_data,
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output core_adc_i0_valid,
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output core_adc_q0_enable,
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output [15:0] core_adc_q0_data,
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output core_adc_q0_valid,
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output core_adc_i1_enable,
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output [15:0] core_adc_i1_data,
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output core_adc_i1_valid,
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output core_adc_q1_enable,
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output [15:0] core_adc_q1_data,
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output core_adc_q1_valid
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);
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2015-06-26 09:04:19 +00:00
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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