99 lines
3.0 KiB
Coq
99 lines
3.0 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input [12:0] gpio_bd_i,
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output [ 7:0] gpio_bd_o,
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// dci_p&n enter the chip
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output dci_p,
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output dci_n,
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// dco_p&n leave the chip
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input dco1_p,
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input dco1_n,
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output [15:0] data_p,
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output [15:0] data_n,
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output spi_clk,
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output spi_dio,
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input spi_do,
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output spi_en);
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [ 2:0] spi_csb;
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// defaults
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assign gpio_bd_o = gpio_o[20:13];
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assign gpio_i[94:13] = gpio_o[94:13];
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assign gpio_i[12: 0] = gpio_bd_i;
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assign spi_en = spi_csb[0];
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// instantiations
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system_wrapper i_system_wrapper (
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (),
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.spi0_csn (spi_csb),
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.spi0_miso (spi_do),
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.spi0_mosi (spi_dio),
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.spi0_sclk (spi_clk),
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.spi1_csn (),
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.spi1_miso (1'b0),
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.spi1_mosi (),
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.spi1_sclk (),
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.dco1_n (dco1_n),
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.dco1_p (dco1_p),
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.dci_n (dci_n),
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.dci_p (dci_p),
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.data_n (data_n),
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.data_p (data_p));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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