pluto_hdl_adi/library/interfaces/interfaces_ip.tcl

###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

# ip
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

adi_if_define if_xcvr_cm
adi_if_ports output    1  enb
adi_if_ports output   12  addr
adi_if_ports output    1  wr
adi_if_ports output   16  wdata
adi_if_ports input    16  rdata
adi_if_ports input     1  ready

adi_if_define if_xcvr_ch
adi_if_ports input     1  pll_locked
adi_if_ports output    1  rst
adi_if_ports output    1  user_ready
adi_if_ports input     1  rst_done
adi_if_ports output    4  prbssel
adi_if_ports output    1  prbsforceerr
adi_if_ports output    1  prbscntreset
adi_if_ports input     1  prbserr
adi_if_ports input     1  prbslocked
adi_if_ports output    1  lpm_dfe_n
adi_if_ports output    3  rate
adi_if_ports output    2  sys_clk_sel
adi_if_ports output    3  out_clk_sel
adi_if_ports output    4  tx_diffctrl
adi_if_ports output    5  tx_postcursor
adi_if_ports output    5  tx_precursor
adi_if_ports output    1  enb
adi_if_ports output   12  addr
adi_if_ports output    1  wr
adi_if_ports output   16  wdata
adi_if_ports input    16  rdata
adi_if_ports input     1  ready
adi_if_ports output    2  bufstatus
adi_if_ports output    1  bufstatus_rst

adi_if_define if_gt_qpll
adi_if_ports output    1  qpll_rst            reset
adi_if_ports output    1  qpll_ref_clk        clock

adi_if_define if_gt_pll
adi_if_ports output    1  cpll_rst_m          reset
adi_if_ports output    1  cpll_ref_clk_in     clock

adi_if_define if_gt_rx
adi_if_ports  output   1  rx_p
adi_if_ports  output   1  rx_n
adi_if_ports  input    1  rx_rst              reset
adi_if_ports  output   1  rx_rst_m            reset
adi_if_ports  input    1  rx_pll_rst          reset
adi_if_ports  input    1  rx_gt_rst           reset
adi_if_ports  output   1  rx_gt_rst_m         reset
adi_if_ports  input    1  rx_pll_locked
adi_if_ports  output   1  rx_pll_locked_m
adi_if_ports  input    1  rx_user_ready
adi_if_ports  output   1  rx_user_ready_m
adi_if_ports  input    1  rx_rst_done
adi_if_ports  output   1  rx_rst_done_m
adi_if_ports  input    1  rx_out_clk          clock
adi_if_ports  output   1  rx_clk              clock
adi_if_ports  output   1  rx_sysref
adi_if_ports  input    1  rx_sync
adi_if_ports  input    1  rx_sof
adi_if_ports  input   32  rx_data
adi_if_ports  input    1  rx_ip_rst           reset
adi_if_ports  output   4  rx_ip_sof
adi_if_ports  output  32  rx_ip_data
adi_if_ports  input    1  rx_ip_sysref
adi_if_ports  output   1  rx_ip_sync
adi_if_ports  input    1  rx_ip_rst_done

adi_if_define if_gt_tx
adi_if_ports  input    1  tx_p
adi_if_ports  input    1  tx_n
adi_if_ports  input    1  tx_rst              reset
adi_if_ports  output   1  tx_rst_m            reset
adi_if_ports  input    1  tx_pll_rst          reset
adi_if_ports  input    1  tx_gt_rst           reset
adi_if_ports  output   1  tx_gt_rst_m         reset
adi_if_ports  input    1  tx_pll_locked
adi_if_ports  output   1  tx_pll_locked_m
adi_if_ports  input    1  tx_user_ready
adi_if_ports  output   1  tx_user_ready_m
adi_if_ports  input    1  tx_rst_done
adi_if_ports  output   1  tx_rst_done_m
adi_if_ports  input    1  tx_out_clk          clock
adi_if_ports  output   1  tx_clk              clock
adi_if_ports  output   1  tx_sysref
adi_if_ports  output   1  tx_sync
adi_if_ports  output  32  tx_data
adi_if_ports  input    1  tx_ip_rst           reset
adi_if_ports  input   32  tx_ip_data
adi_if_ports  input    1  tx_ip_sysref
adi_if_ports  input    1  tx_ip_sync
adi_if_ports  input    1  tx_ip_rst_done

adi_if_define if_gt_rx_ksig
adi_if_ports  output   4  rx_gt_ilas_f
adi_if_ports  output   4  rx_gt_ilas_q
adi_if_ports  output   4  rx_gt_ilas_a
adi_if_ports  output   4  rx_gt_ilas_r
adi_if_ports  output   4  rx_gt_cgs_k

adi_if_define if_do_ctrl
adi_if_ports  output   1  request_enable
adi_if_ports  output   1  request_valid
adi_if_ports  input    1  request_ready
adi_if_ports  output  -1  request_length
adi_if_ports  output  -1  response_measured_length
adi_if_ports  input    1  response_eot
adi_if_ports  input    1  status_underflow
adi_if_ports  input    1  status_overflow
Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com> 2023-07-06 12:08:22 +00:00			`###############################################################################`
			`## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.`
			`### SPDX short identifier: ADIBSD`
			`###############################################################################`
interfaces_ip: added 2015-08-14 15:24:27 +00:00
Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com> 2023-07-06 12:08:22 +00:00			`# ip`
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips 2022-07-12 11:06:15 +00:00			`source ../../scripts/adi_env.tcl`
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2018-08-14 09:59:39 +00:00			`source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl`
interfaces_ip: added 2015-08-14 15:24:27 +00:00
interfaces: added xcvr interfaces 2016-06-17 16:00:15 +00:00			`adi_if_define if_xcvr_cm`
			`adi_if_ports output 1 enb`
			`adi_if_ports output 12 addr`
interfaces_ip.tcl: Delete trailing white spaces 2018-10-04 08:33:57 +00:00			`adi_if_ports output 1 wr`
interfaces: added xcvr interfaces 2016-06-17 16:00:15 +00:00			`adi_if_ports output 16 wdata`
			`adi_if_ports input 16 rdata`
			`adi_if_ports input 1 ready`

			`adi_if_define if_xcvr_ch`
			`adi_if_ports input 1 pll_locked`
			`adi_if_ports output 1 rst`
			`adi_if_ports output 1 user_ready`
			`adi_if_ports input 1 rst_done`
xilinx:adxcvr: PRBS support The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal PRBS generators and checkers allowing the testing the multi-gigabit serial link at the physical layer without the need of the link layer bringup. 2020-12-18 14:43:28 +00:00			`adi_if_ports output 4 prbssel`
			`adi_if_ports output 1 prbsforceerr`
			`adi_if_ports output 1 prbscntreset`
			`adi_if_ports input 1 prbserr`
			`adi_if_ports input 1 prbslocked`
interfaces: added xcvr interfaces 2016-06-17 16:00:15 +00:00			`adi_if_ports output 1 lpm_dfe_n`
			`adi_if_ports output 3 rate`
			`adi_if_ports output 2 sys_clk_sel`
			`adi_if_ports output 3 out_clk_sel`
axi\|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576) 2018-10-01 15:36:39 +00:00			`adi_if_ports output 4 tx_diffctrl`
			`adi_if_ports output 5 tx_postcursor`
			`adi_if_ports output 5 tx_precursor`
interfaces: added xcvr interfaces 2016-06-17 16:00:15 +00:00			`adi_if_ports output 1 enb`
			`adi_if_ports output 12 addr`
			`adi_if_ports output 1 wr`
			`adi_if_ports output 16 wdata`
			`adi_if_ports input 16 rdata`
			`adi_if_ports input 1 ready`
adxcvr: Increase version to 17.5.a Add suport for XCVR phase adjust buffer status: - Expose TXBUFSTATUS and RXBUFSTATUS - Create RXBUFSTATUS_RST flag for clearing RXBUFSTATUS 2021-10-01 14:41:30 +00:00			`adi_if_ports output 2 bufstatus`
			`adi_if_ports output 1 bufstatus_rst`
interfaces: added xcvr interfaces 2016-06-17 16:00:15 +00:00
interfaces-- transceiver cores 2015-08-14 19:33:36 +00:00			`adi_if_define if_gt_qpll`
			`adi_if_ports output 1 qpll_rst reset`
			`adi_if_ports output 1 qpll_ref_clk clock`
interfaces_ip: added 2015-08-14 15:24:27 +00:00
interfaces-- transceiver cores 2015-08-14 19:33:36 +00:00			`adi_if_define if_gt_pll`
			`adi_if_ports output 1 cpll_rst_m reset`
			`adi_if_ports output 1 cpll_ref_clk_in clock`
interfaces_ip: added 2015-08-14 15:24:27 +00:00
interfaces-- transceiver cores 2015-08-14 19:33:36 +00:00			`adi_if_define if_gt_rx`
interfaces_ip.tcl: Delete trailing white spaces 2018-10-04 08:33:57 +00:00			`adi_if_ports output 1 rx_p`
			`adi_if_ports output 1 rx_n`
interfaces_ip: added 2015-08-14 15:24:27 +00:00			`adi_if_ports input 1 rx_rst reset`
			`adi_if_ports output 1 rx_rst_m reset`
up_gt: separate pll resets to tx/rx 2015-10-02 16:53:23 +00:00			`adi_if_ports input 1 rx_pll_rst reset`
interfaces_ip: added 2015-08-14 15:24:27 +00:00			`adi_if_ports input 1 rx_gt_rst reset`
			`adi_if_ports output 1 rx_gt_rst_m reset`
interfaces_ip.tcl: Delete trailing white spaces 2018-10-04 08:33:57 +00:00			`adi_if_ports input 1 rx_pll_locked`
			`adi_if_ports output 1 rx_pll_locked_m`
			`adi_if_ports input 1 rx_user_ready`
			`adi_if_ports output 1 rx_user_ready_m`
			`adi_if_ports input 1 rx_rst_done`
			`adi_if_ports output 1 rx_rst_done_m`
interfaces_ip: added 2015-08-14 15:24:27 +00:00			`adi_if_ports input 1 rx_out_clk clock`
			`adi_if_ports output 1 rx_clk clock`
interfaces_ip.tcl: Delete trailing white spaces 2018-10-04 08:33:57 +00:00			`adi_if_ports output 1 rx_sysref`
			`adi_if_ports input 1 rx_sync`
			`adi_if_ports input 1 rx_sof`
			`adi_if_ports input 32 rx_data`
interfaces_ip: added 2015-08-14 15:24:27 +00:00			`adi_if_ports input 1 rx_ip_rst reset`
interfaces_ip.tcl: Delete trailing white spaces 2018-10-04 08:33:57 +00:00			`adi_if_ports output 4 rx_ip_sof`
			`adi_if_ports output 32 rx_ip_data`
			`adi_if_ports input 1 rx_ip_sysref`
			`adi_if_ports output 1 rx_ip_sync`
			`adi_if_ports input 1 rx_ip_rst_done`
interfaces_ip: added 2015-08-14 15:24:27 +00:00
interfaces-- transceiver cores 2015-08-14 19:33:36 +00:00			`adi_if_define if_gt_tx`
			`adi_if_ports input 1 tx_p`
			`adi_if_ports input 1 tx_n`
			`adi_if_ports input 1 tx_rst reset`
			`adi_if_ports output 1 tx_rst_m reset`
up_gt: separate pll resets to tx/rx 2015-10-02 16:53:23 +00:00			`adi_if_ports input 1 tx_pll_rst reset`
interfaces-- transceiver cores 2015-08-14 19:33:36 +00:00			`adi_if_ports input 1 tx_gt_rst reset`
			`adi_if_ports output 1 tx_gt_rst_m reset`
interfaces_ip.tcl: Delete trailing white spaces 2018-10-04 08:33:57 +00:00			`adi_if_ports input 1 tx_pll_locked`
			`adi_if_ports output 1 tx_pll_locked_m`
			`adi_if_ports input 1 tx_user_ready`
			`adi_if_ports output 1 tx_user_ready_m`
			`adi_if_ports input 1 tx_rst_done`
			`adi_if_ports output 1 tx_rst_done_m`
interfaces-- transceiver cores 2015-08-14 19:33:36 +00:00			`adi_if_ports input 1 tx_out_clk clock`
			`adi_if_ports output 1 tx_clk clock`
interfaces_ip.tcl: Delete trailing white spaces 2018-10-04 08:33:57 +00:00			`adi_if_ports output 1 tx_sysref`
			`adi_if_ports output 1 tx_sync`
			`adi_if_ports output 32 tx_data`
interfaces-- transceiver cores 2015-08-14 19:33:36 +00:00			`adi_if_ports input 1 tx_ip_rst reset`
interfaces_ip.tcl: Delete trailing white spaces 2018-10-04 08:33:57 +00:00			`adi_if_ports input 32 tx_ip_data`
			`adi_if_ports input 1 tx_ip_sysref`
			`adi_if_ports input 1 tx_ip_sync`
			`adi_if_ports input 1 tx_ip_rst_done`
interfaces-- transceiver cores 2015-08-14 19:33:36 +00:00
			`adi_if_define if_gt_rx_ksig`
			`adi_if_ports output 4 rx_gt_ilas_f`
			`adi_if_ports output 4 rx_gt_ilas_q`
			`adi_if_ports output 4 rx_gt_ilas_a`
			`adi_if_ports output 4 rx_gt_ilas_r`
			`adi_if_ports output 4 rx_gt_cgs_k`
interfaces_ip: added 2015-08-14 15:24:27 +00:00
interfaces: Data offload control interface Have a control interface between the data offload and storage units. 2022-04-06 07:28:17 +00:00			`adi_if_define if_do_ctrl`
			`adi_if_ports output 1 request_enable`
			`adi_if_ports output 1 request_valid`
			`adi_if_ports input 1 request_ready`
			`adi_if_ports output -1 request_length`
			`adi_if_ports output -1 response_measured_length`
			`adi_if_ports input 1 response_eot`
			`adi_if_ports input 1 status_underflow`
			`adi_if_ports input 1 status_overflow`