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pluto_hdl_adi/library/util_dacfifo/util_dacfifo_ip.tcl

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dacfifo: added
2015-04-07 19:55:29 +00:00
# ip
source ../scripts/adi_env.tcl
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2018-08-14 09:59:39 +00:00
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
dacfifo: added
2015-04-07 19:55:29 +00:00
adi_ip_create util_dacfifo
adi_ip_files util_dacfifo [list \
"$ad_hdl_dir/library/common/ad_mem.v" \
util_dacfifo: Update the bypass logic
2018-08-21 12:59:25 +00:00
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
util_dacfifo: Integrate grey coder/decoder module The grey coder/decoder function was limited to 10 bits, and this resulted an unwanted limitation of the FIFO size. Using this module, the coder/decoder data width can be adjusted to the current address width.
2017-10-05 11:20:54 +00:00
"$ad_hdl_dir/library/common/ad_b2g.v" \
"$ad_hdl_dir/library/common/ad_g2b.v" \
util_dacfifo: Add constraints file
2016-04-12 10:21:50 +00:00
"util_dacfifo.v" \
util_dacfifo: Update the bypass logic
2018-08-21 12:59:25 +00:00
"util_dacfifo_bypass.v" \
util_dacfifo: set OOC default clock constraints Out of Context constraints are needed for timing driven synthesis as for avoiding critical warnings due clock queries. The memory from the FIFO is inferred in different ways for high clock speeds. Assume the highest frequency for all projects.
2019-04-08 14:44:53 +00:00
"util_dacfifo_ooc.ttcl" \
util_dacfifo: Add constraints file
2016-04-12 10:21:50 +00:00
"util_dacfifo_constr.xdc"]
dacfifo: added
2015-04-07 19:55:29 +00:00
util_dacfifo: set OOC default clock constraints Out of Context constraints are needed for timing driven synthesis as for avoiding critical warnings due clock queries. The memory from the FIFO is inferred in different ways for high clock speeds. Assume the highest frequency for all projects.
2019-04-08 14:44:53 +00:00
dacfifo: added
2015-04-07 19:55:29 +00:00
adi_ip_properties_lite util_dacfifo
util_dacfifo: set OOC default clock constraints Out of Context constraints are needed for timing driven synthesis as for avoiding critical warnings due clock queries. The memory from the FIFO is inferred in different ways for high clock speeds. Assume the highest frequency for all projects.
2019-04-08 14:44:53 +00:00
adi_ip_ttcl util_dacfifo "util_dacfifo_ooc.ttcl"
util_dacfifo: Infer clock and reset signals
2018-04-03 07:13:05 +00:00
ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
dacfifo: added
2015-04-07 19:55:29 +00:00
ipx::save_core [ipx::current_core]