zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc

53 lines
3.2 KiB
Plaintext
Raw Normal View History

axi_dacfifo: Fix constraints
2017-02-21 12:45:18 +00:00
set_property ASYNC_REG TRUE \
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
[get_cells -hier *dma_mem_*_m*] \
[get_cells -hier *axi_xfer_*_m*] \
[get_cells -hier *axi_mem_*_m*] \
[get_cells -hier *axi_dma_*_m*] \
[get_cells -hier *dac_mem_*_m*] \
[get_cells -hier *dac_xfer_*_m*] \
[get_cells -hier *dac_last_*_m*] \
[get_cells -hier *dac_bypass_m*]
axi_dacfifo: Update the constraints
2016-05-24 15:09:27 +00:00
axi_dacfifo: Rewrote constraints to be more specific Some of the wildcards matched too many paths and disabled the timing checks on intraclock paths.
2018-02-19 08:15:03 +00:00
# AXI clk to DMA clk
set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_raddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */dma_mem_raddr_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_last_read_toggle* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */dma_mem_last_read_toggle_m_* && IS_SEQUENTIAL}]
# DAC clk to DMA clk
set_false_path -from [get_cells -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */dma_mem_raddr_m1_* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ */dma_rst_m1_reg && IS_SEQUENTIAL}]
# DMA clk to AXI clk
set_false_path -from [get_cells -hier -filter {name =~ */dma_last_beats* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */axi_dma_last_beats_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */axi_mem_waddr_m1* && IS_SEQUENTIAL}]
#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
set_false_path -through [get_pins -hier -filter {name =~ */axi_xfer_req_m_reg[0]/D}]
# DAC clk to AXI clk
set_false_path -from [get_cells -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */axi_mem_raddr_m1* && IS_SEQUENTIAL}]
# DMA clk to DAC clk
set_false_path -from [get_cells -hier -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ */dma_last_beats* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */dac_last_beats_m* && IS_SEQUENTIAL}]
#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
set_false_path -through [get_pins -hier -filter {name =~ */dac_xfer_out_m1_reg*/D}]
# AXI clk to DAC clk
set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_laddr* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */dac_mem_laddr* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_laddr_toggle* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */dac_mem_laddr_toggle_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_waddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}]
#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
set_false_path -through [get_pins -hier -filter {name =~ */dac_xfer_req_m_reg[0]/D}]
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00