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pluto_hdl_adi/projects/common/a5gt/a5gt_system_bd.qsys

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a5gt- base system
2015-07-22 19:04:59 +00:00
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
element a5gt_system_bd
a5gt- base system
2015-07-22 19:04:59 +00:00
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
element cpu_clk
a5gt- base system
2015-07-22 19:04:59 +00:00
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
datum _sortIndex
a5gt- base system
2015-07-22 19:04:59 +00:00
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "21";
type = "int";
}
}
element cpu_reset
{
datum _sortIndex
{
value = "22";
type = "int";
a5gt- base system
2015-07-22 19:04:59 +00:00
}
}
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
element mem_clk
a5gt- base system
2015-07-22 19:04:59 +00:00
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "19";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
a5gt- base system
2015-07-22 19:04:59 +00:00
}
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
element mem_rst
a5gt- base system
2015-07-22 19:04:59 +00:00
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "20";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
a5gt- base system
2015-07-22 19:04:59 +00:00
}
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
element sys_clk
a5gt- base system
2015-07-22 19:04:59 +00:00
{
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
datum _sortIndex
a5gt- base system
2015-07-22 19:04:59 +00:00
{
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
value = "0";
type = "int";
a5gt- base system
2015-07-22 19:04:59 +00:00
}
}
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
element sys_cpu
a5gt- base system
2015-07-22 19:04:59 +00:00
{
datum _sortIndex
{
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
value = "3";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
}
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
element sys_cpu.debug_mem_slave
a5gt- base system
2015-07-22 19:04:59 +00:00
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "354473984";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
element sys_cpu_interconnect
a5gt- base system
2015-07-22 19:04:59 +00:00
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "17";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
a5gt- base system
2015-07-22 19:04:59 +00:00
}
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
element sys_cpu_interconnect.s0
a5gt- base system
2015-07-22 19:04:59 +00:00
{
datum baseAddress
{
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
value = "536870912";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
element sys_ddr3_cntrl
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "6";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
}
element sys_ddr3_cntrl.avl
{
datum _lockedAddress
{
value = "0";
type = "boolean";
}
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "0";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
element sys_ethernet
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "7";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
datum sopceditor_expanded
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "0";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "boolean";
}
}
element sys_ethernet.control_port
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "354476032";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
element sys_ethernet_dma_rx
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "8";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
a5gt- base system
2015-07-22 19:04:59 +00:00
}
element sys_ethernet_dma_rx.csr
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "354477120";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
element sys_ethernet_dma_rx.descriptor_slave
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "354477152";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
element sys_ethernet_dma_rx.response
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "354477184";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
element sys_ethernet_dma_tx
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "9";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
a5gt- base system
2015-07-22 19:04:59 +00:00
}
element sys_ethernet_dma_tx.csr
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "354477056";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
element sys_ethernet_dma_tx.descriptor_slave
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "354477088";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
element sys_gpio
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "14";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
datum sopceditor_expanded
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "0";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "boolean";
}
}
element sys_gpio.s1
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "354477248";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
element sys_gpio_bd
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "15";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
a5gt- base system
2015-07-22 19:04:59 +00:00
}
element sys_gpio_bd.s1
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "354477344";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
element sys_id
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "13";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
datum sopceditor_expanded
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "0";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "boolean";
}
}
element sys_id.control_slave
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "354477272";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
element sys_int_mem
{
datum _sortIndex
{
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
value = "4";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
}
element sys_int_mem.s1
{
datum _lockedAddress
{
value = "0";
type = "boolean";
}
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "352321536";
type = "String";
}
}
element sys_int_mem.s2
{
datum baseAddress
{
value = "352321536";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
element sys_intr
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "23";
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
type = "int";
}
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
}
element sys_mem_interconnect
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "18";
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
type = "int";
}
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
}
a5gt- base system
2015-07-22 19:04:59 +00:00
element sys_pll
{
datum _sortIndex
{
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
value = "2";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "int";
}
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
}
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
element sys_rst
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
a5gt- base system
2015-07-22 19:04:59 +00:00
element sys_spi
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "16";
a5gt- base system
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type = "int";
}
datum sopceditor_expanded
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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value = "0";
a5gt- base system
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type = "boolean";
}
}
element sys_spi.spi_control_port
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
value = "354477312";
a5gt- base system
2015-07-22 19:04:59 +00:00
type = "String";
}
}
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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element sys_tcm_mem
a5gt- base system
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{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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value = "5";
a5gt- base system
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type = "int";
}
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
}
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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element sys_tcm_mem.s1
{
datum baseAddress
{
value = "354467840";
type = "String";
}
}
element sys_tcm_mem.s2
{
datum baseAddress
{
value = "354467840";
type = "String";
}
}
element sys_timer
{
datum _sortIndex
{
value = "11";
type = "int";
}
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
}
a5gt- base system
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element sys_timer.s1
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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value = "354477216";
type = "String";
}
}
element sys_timer_2nd
{
datum _sortIndex
{
value = "12";
type = "int";
}
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
}
element sys_timer_2nd.s1
{
datum baseAddress
{
value = "354477376";
a5gt- base system
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type = "String";
}
}
element sys_uart
{
datum _sortIndex
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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value = "10";
a5gt- base system
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type = "int";
}
datum sopceditor_expanded
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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value = "0";
a5gt- base system
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type = "boolean";
}
}
element sys_uart.avalon_jtag_slave
{
datum baseAddress
{
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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value = "354477280";
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type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="FIFO" />
<parameter name="device" value="5AGTFD7K3F40I3" />
<parameter name="deviceFamily" value="Arria V" />
<parameter name="deviceSpeedGrade" value="3_H3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="2" />
a5gt-base: initial updates
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<parameter name="projectName" value="" />
a5gt- base system
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<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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<interface name="cpu_clk" internal="cpu_clk.out_clk" type="clock" dir="start" />
<interface
name="cpu_rst"
internal="cpu_reset.out_reset"
type="reset"
dir="start" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<interface name="mem_clk" internal="mem_clk.out_clk" type="clock" dir="start" />
<interface name="mem_rst" internal="mem_rst.out_reset" type="reset" dir="start" />
a5gt- base system
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<interface
name="sys_125m_clk"
internal="sys_pll.outclk0"
type="clock"
dir="start" />
<interface
name="sys_25m_clk"
internal="sys_pll.outclk1"
type="clock"
dir="start" />
<interface
name="sys_2m5_clk"
internal="sys_pll.outclk2"
type="clock"
dir="start" />
a5gt-base: initial updates
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<interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
<interface
name="sys_cpu_interconnect_m0"
internal="sys_cpu_interconnect.m0"
type="avalon"
dir="start" />
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<interface
name="sys_ddr3_oct"
internal="sys_ddr3_cntrl.oct"
type="conduit"
dir="end" />
<interface
name="sys_ddr3_phy"
internal="sys_ddr3_cntrl.memory"
type="conduit"
dir="end" />
<interface
name="sys_ethernet_mdio"
internal="sys_ethernet.mac_mdio_connection"
type="conduit"
dir="end" />
<interface
name="sys_ethernet_rgmii"
internal="sys_ethernet.mac_rgmii_connection"
type="conduit"
dir="end" />
<interface
name="sys_ethernet_rx_clk"
internal="sys_ethernet.pcs_mac_rx_clock_connection"
type="clock"
dir="end" />
<interface
name="sys_ethernet_status"
internal="sys_ethernet.mac_status_connection"
type="conduit"
dir="end" />
<interface
name="sys_ethernet_tx_clk"
internal="sys_ethernet.pcs_mac_tx_clock_connection"
type="clock"
dir="end" />
<interface
name="sys_gpio"
internal="sys_gpio.external_connection"
type="conduit"
dir="end" />
<interface
name="sys_gpio_bd"
internal="sys_gpio_bd.external_connection"
type="conduit"
dir="end" />
a5gt-base: initial updates
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<interface
name="sys_intr"
internal="sys_intr.receiver_irq"
type="interrupt"
dir="start" />
<interface
name="sys_mem_interconnect_s0"
internal="sys_mem_interconnect.s0"
type="avalon"
dir="end" />
a5gt- base system
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<interface
name="sys_pll_locked"
internal="sys_pll.locked"
type="conduit"
dir="end" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
a5gt- base system
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<interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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<module name="cpu_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="DERIVED_CLOCK_RATE" value="100000000" />
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
a5gt- base system
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</module>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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<module
name="cpu_reset"
kind="altera_reset_bridge"
version="15.1"
enabled="1">
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="ACTIVE_LOW_RESET" value="0" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="NUM_RESET_OUTPUTS" value="1" />
<parameter name="SYNCHRONOUS_EDGES" value="none" />
<parameter name="USE_RESET_REQUEST" value="0" />
</module>
<module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="100000000" />
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module>
<module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="NUM_RESET_OUTPUTS" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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<parameter name="SYNCHRONOUS_EDGES" value="none" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="USE_RESET_REQUEST" value="0" />
a5gt- base system
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</module>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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<module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="1000000000" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</module>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<module name="sys_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="14" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="14" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="breakOffset" value="32" />
<parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
<parameter name="cdx_enabled" value="false" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="clockFrequency" value="100000000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="cpuArchRev" value="1" />
<parameter name="cpuID" value="0" />
<parameter name="cpuReset" value="false" />
<parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="dataAddrWidth" value="30" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='sys_int_mem.s1' start='0x15000000' end='0x150C0000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x1520D800' end='0x1520E000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x1520E000' end='0x1520E400' type='altera_eth_tse.control_port' /><slave name='sys_ethernet_dma_tx.csr' start='0x1520E400' end='0x1520E420' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x1520E420' end='0x1520E440' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_rx.csr' start='0x1520E440' end='0x1520E460' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x1520E460' end='0x1520E480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_rx.response' start='0x1520E480' end='0x1520E488' type='altera_msgdma.response' /><slave name='sys_timer.s1' start='0x1520E4A0' end='0x1520E4C0' type='altera_avalon_timer.s1' /><slave name='sys_gpio.s1' start='0x1520E4C0' end='0x1520E4D0' type='altera_avalon_pio.s1' /><slave name='sys_id.control_slave' start='0x1520E4D8' end='0x1520E4E0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x1520E4E0' end='0x1520E4E8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_spi.spi_control_port' start='0x1520E500' end='0x1520E520' type='altera_avalon_spi.spi_control_port' /><slave name='sys_gpio_bd.s1' start='0x1520E520' end='0x1520E530' type='altera_avalon_pio.s1' /><slave name='sys_timer_2nd.s1' start='0x1520E540' end='0x1520E560' type='altera_avalon_timer.s1' /><slave name='sys_cpu_interconnect.s0' start='0x20000000' end='0x21000000' type='altera_avalon_mm_bridge.s0' /></address-map>]]></parameter>
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
<parameter name="data_master_paddr_size" value="0" />
<parameter name="dcache_bursts" value="false" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="dcache_numTCDM" value="1" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="dcache_ramBlockType" value="Automatic" />
<parameter name="dcache_size" value="32768" />
<parameter name="dcache_tagramBlockType" value="Automatic" />
<parameter name="dcache_victim_buf_impl" value="ram" />
<parameter name="debug_OCIOnchipTrace" value="_128" />
<parameter name="debug_assignJtagInstanceID" value="false" />
<parameter name="debug_datatrigger" value="0" />
<parameter name="debug_debugReqSignals" value="false" />
<parameter name="debug_enabled" value="true" />
<parameter name="debug_hwbreakpoint" value="0" />
<parameter name="debug_jtagInstanceID" value="0" />
<parameter name="debug_traceStorage" value="onchip_trace" />
<parameter name="debug_traceType" value="none" />
<parameter name="debug_triggerArming" value="true" />
<parameter name="deviceFamilyName" value="Arria V" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="dividerType" value="no_div" />
<parameter name="exceptionOffset" value="32" />
<parameter name="exceptionSlave" value="sys_ddr3_cntrl.avl" />
<parameter name="faAddrWidth" value="1" />
<parameter name="faSlaveMapParam" value="" />
<parameter name="fa_cache_line" value="2" />
<parameter name="fa_cache_linesize" value="0" />
<parameter name="flash_instruction_master_paddr_base" value="0" />
<parameter name="flash_instruction_master_paddr_size" value="0" />
<parameter name="icache_burstType" value="None" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="icache_numTCIM" value="1" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="icache_ramBlockType" value="Automatic" />
<parameter name="icache_size" value="32768" />
<parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="impl" value="Fast" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="instAddrWidth" value="29" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='sys_int_mem.s2' start='0x15000000' end='0x150C0000' type='altera_avalon_onchip_memory2.s2' /><slave name='sys_cpu.debug_mem_slave' start='0x1520D800' end='0x1520E000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
<parameter name="instruction_master_high_performance_paddr_base" value="0" />
<parameter name="instruction_master_high_performance_paddr_size" value="0" />
<parameter name="instruction_master_paddr_base" value="0" />
<parameter name="instruction_master_paddr_size" value="0" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="internalIrqMaskSystemInfo" value="65535" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="io_regionbase" value="0" />
<parameter name="io_regionsize" value="0" />
<parameter name="master_addr_map" value="false" />
<parameter name="mmu_TLBMissExcOffset" value="4096" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="mmu_TLBMissExcSlave" value="sys_int_mem.s2" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="mmu_autoAssignTlbPtrSz" value="false" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="mmu_enabled" value="true" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="mmu_processIDNumBits" value="8" />
<parameter name="mmu_ramBlockType" value="Automatic" />
<parameter name="mmu_tlbNumWays" value="16" />
<parameter name="mmu_tlbPtrSz" value="7" />
<parameter name="mmu_udtlbNumEntries" value="6" />
<parameter name="mmu_uitlbNumEntries" value="4" />
<parameter name="mpu_enabled" value="false" />
<parameter name="mpu_minDataRegionSize" value="12" />
<parameter name="mpu_minInstRegionSize" value="12" />
<parameter name="mpu_numOfDataRegion" value="8" />
<parameter name="mpu_numOfInstRegion" value="8" />
<parameter name="mpu_useLimit" value="false" />
<parameter name="mpx_enabled" value="false" />
<parameter name="mul_32_impl" value="3" />
<parameter name="mul_64_impl" value="0" />
<parameter name="mul_shift_choice" value="0" />
<parameter name="ocimem_ramBlockType" value="Automatic" />
<parameter name="ocimem_ramInit" value="false" />
<parameter name="regfile_ramBlockType" value="Automatic" />
<parameter name="resetOffset" value="0" />
<parameter name="resetSlave" value="sys_ddr3_cntrl.avl" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="setting_HBreakTest" value="false" />
<parameter name="setting_HDLSimCachesCleared" value="true" />
<parameter name="setting_activateMonitors" value="true" />
<parameter name="setting_activateTestEndChecker" value="false" />
<parameter name="setting_activateTrace" value="true" />
<parameter name="setting_allow_break_inst" value="false" />
<parameter name="setting_alwaysEncrypt" value="true" />
<parameter name="setting_asic_add_scan_mode_input" value="false" />
<parameter name="setting_asic_enabled" value="false" />
<parameter name="setting_asic_synopsys_translate_on_off" value="false" />
<parameter name="setting_asic_third_party_synthesis" value="false" />
<parameter name="setting_avalonDebugPortPresent" value="false" />
<parameter name="setting_bhtPtrSz" value="8" />
<parameter name="setting_bigEndian" value="false" />
<parameter name="setting_branchpredictiontype" value="Dynamic" />
<parameter name="setting_breakslaveoveride" value="false" />
<parameter name="setting_clearXBitsLDNonBypass" value="true" />
<parameter name="setting_dc_ecc_present" value="false" />
<parameter name="setting_disable_tmr_inj" value="false" />
<parameter name="setting_disableocitrace" value="false" />
<parameter name="setting_dtcm_ecc_present" value="false" />
<parameter name="setting_ecc_present" value="false" />
<parameter name="setting_ecc_sim_test_ports" value="false" />
<parameter name="setting_exportHostDebugPort" value="false" />
<parameter name="setting_exportPCB" value="false" />
<parameter name="setting_export_large_RAMs" value="false" />
<parameter name="setting_exportdebuginfo" value="false" />
<parameter name="setting_exportvectors" value="false" />
<parameter name="setting_fast_register_read" value="false" />
<parameter name="setting_ic_ecc_present" value="true" />
<parameter name="setting_interruptControllerType" value="Internal" />
<parameter name="setting_itcm_ecc_present" value="false" />
<parameter name="setting_mmu_ecc_present" value="true" />
<parameter name="setting_oci_export_jtag_signals" value="false" />
<parameter name="setting_oci_version" value="1" />
<parameter name="setting_preciseIllegalMemAccessException" value="false" />
<parameter name="setting_removeRAMinit" value="false" />
<parameter name="setting_rf_ecc_present" value="true" />
<parameter name="setting_shadowRegisterSets" value="0" />
<parameter name="setting_showInternalSettings" value="false" />
<parameter name="setting_showUnpublishedSettings" value="false" />
<parameter name="setting_support31bitdcachebypass" value="true" />
<parameter name="setting_usedesignware" value="false" />
<parameter name="shift_rot_impl" value="0" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
<parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s1' start='0x1520C000' end='0x1520D000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
<parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s2' start='0x1520C000' end='0x1520D000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
<parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
<parameter name="tmr_enabled" value="false" />
<parameter name="tracefilename" value="" />
<parameter name="userDefinedSettings" value="" />
</module>
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<module
name="sys_cpu_interconnect"
kind="altera_avalon_mm_bridge"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
enabled="1">
<parameter name="ADDRESS_UNITS" value="SYMBOLS" />
<parameter name="ADDRESS_WIDTH" value="24" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
<parameter name="DATA_WIDTH" value="32" />
<parameter name="LINEWRAPBURSTS" value="0" />
<parameter name="MAX_BURST_SIZE" value="1" />
<parameter name="MAX_PENDING_RESPONSES" value="4" />
<parameter name="PIPELINE_COMMAND" value="1" />
<parameter name="PIPELINE_RESPONSE" value="1" />
<parameter name="SYMBOL_WIDTH" value="8" />
<parameter name="SYSINFO_ADDR_WIDTH" value="10" />
<parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
<parameter name="USE_RESPONSE" value="0" />
</module>
a5gt- base system
2015-07-22 19:04:59 +00:00
<module
name="sys_ddr3_cntrl"
kind="altera_mem_if_ddr3_emif"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
enabled="1">
<parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
<parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
<parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
<parameter name="AC_PACKAGE_DESKEW" value="false" />
<parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
<parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
<parameter name="ADDR_ORDER" value="0" />
<parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
<parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
<parameter name="ADVANCED_CK_PHASES" value="false" />
<parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
<parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
<parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
<parameter name="AP_MODE" value="false" />
<parameter name="AP_MODE_EN" value="0" />
<parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
<parameter name="AUTO_PD_CYCLES" value="0" />
<parameter name="AUTO_POWERDN_EN" value="false" />
<parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
<parameter name="AVL_MAX_SIZE" value="256" />
<parameter name="BYTE_ENABLE" value="true" />
<parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
<parameter name="CALIBRATION_MODE" value="Skip" />
<parameter name="CALIB_REG_WIDTH" value="8" />
<parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
<parameter name="CFG_REORDER_DATA" value="true" />
<parameter name="CFG_TCCD_NS" value="2.5" />
<parameter name="COMMAND_PHASE" value="0.0" />
<parameter name="CONTROLLER_LATENCY" value="5" />
<parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
<parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
<parameter name="CTL_AUTOPCH_EN" value="false" />
<parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
<parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
<parameter name="CTL_CSR_ENABLED" value="false" />
<parameter name="CTL_CSR_READ_ONLY" value="1" />
<parameter name="CTL_DEEP_POWERDN_EN" value="false" />
<parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
<parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
<parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
<parameter name="CTL_ECC_ENABLED" value="false" />
<parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
<parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
<parameter name="CTL_HRB_ENABLED" value="false" />
<parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
<parameter name="CTL_SELF_REFRESH_EN" value="false" />
<parameter name="CTL_USR_REFRESH_EN" value="false" />
<parameter name="CTL_ZQCAL_EN" value="false" />
<parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
<parameter name="DAT_DATA_WIDTH" value="32" />
<parameter name="DEBUG_MODE" value="false" />
<parameter name="DEVICE_DEPTH" value="1" />
<parameter name="DEVICE_FAMILY_PARAM" value="" />
<parameter name="DISABLE_CHILD_MESSAGING" value="false" />
<parameter name="DISCRETE_FLY_BY" value="true" />
<parameter name="DLL_SHARING_MODE" value="None" />
<parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
<parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
<parameter name="DUPLICATE_AC" value="false" />
<parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
<parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
<parameter name="ENABLE_BONDING" value="false" />
<parameter name="ENABLE_BURST_MERGE" value="false" />
<parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
<parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
<parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
<parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
<parameter name="ENABLE_EXTRA_REPORTING" value="false" />
<parameter name="ENABLE_ISS_PROBES" value="false" />
<parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
<parameter name="ENABLE_NON_DES_CAL" value="false" />
<parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
<parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
<parameter name="ENABLE_USER_ECC" value="false" />
<parameter name="EXPORT_AFI_HALF_CLK" value="false" />
<parameter name="EXTRA_SETTINGS" value="" />
<parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
<parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
<parameter name="FORCE_DQS_TRACKING" value="AUTO" />
<parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
<parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
<parameter name="FORCE_SHADOW_REGS" value="AUTO" />
<parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
<parameter name="HARD_EMIF" value="false" />
<parameter name="HCX_COMPAT_MODE" value="false" />
<parameter name="HHP_HPS" value="false" />
<parameter name="HHP_HPS_SIMULATION" value="false" />
<parameter name="HHP_HPS_VERIFICATION" value="false" />
<parameter name="HPS_PROTOCOL" value="DEFAULT" />
<parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
<parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
<parameter name="IS_ES_DEVICE" value="false" />
<parameter name="LOCAL_ID_WIDTH" value="8" />
<parameter name="LRDIMM_EXTENDED_CONFIG" value="0x0" />
<parameter name="MARGIN_VARIATION_TEST" value="false" />
<parameter name="MAX_PENDING_RD_CMD" value="32" />
<parameter name="MAX_PENDING_WR_CMD" value="16" />
<parameter name="MEM_ASR" value="Manual" />
<parameter name="MEM_ATCL" value="Disabled" />
<parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
<parameter name="MEM_BANKADDR_WIDTH" value="3" />
<parameter name="MEM_BL" value="OTF" />
<parameter name="MEM_BT" value="Sequential" />
<parameter name="MEM_CK_PHASE" value="0.0" />
<parameter name="MEM_CK_WIDTH" value="1" />
<parameter name="MEM_CLK_EN_WIDTH" value="1" />
<parameter name="MEM_CLK_FREQ" value="400.0" />
<parameter name="MEM_CLK_FREQ_MAX" value="666.667" />
<parameter name="MEM_COL_ADDR_WIDTH" value="10" />
<parameter name="MEM_CS_WIDTH" value="1" />
<parameter name="MEM_DEVICE" value="MISSING_MODEL" />
<parameter name="MEM_DLL_EN" value="true" />
<parameter name="MEM_DQ_PER_DQS" value="8" />
<parameter name="MEM_DQ_WIDTH" value="64" />
<parameter name="MEM_DRV_STR" value="RZQ/6" />
<parameter name="MEM_FORMAT" value="DISCRETE" />
<parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
<parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
<parameter name="MEM_IF_DM_PINS_EN" value="true" />
<parameter name="MEM_IF_DQSN_EN" value="true" />
<parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
<parameter name="MEM_INIT_EN" value="false" />
<parameter name="MEM_INIT_FILE" value="" />
<parameter name="MEM_MIRROR_ADDRESSING" value="0" />
<parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
<parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
<parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
<parameter name="MEM_PD" value="DLL off" />
<parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
<parameter name="MEM_ROW_ADDR_WIDTH" value="12" />
<parameter name="MEM_RTT_NOM" value="RZQ/6" />
<parameter name="MEM_RTT_WR" value="RZQ/4" />
<parameter name="MEM_SRT" value="Normal" />
<parameter name="MEM_TCL" value="11" />
<parameter name="MEM_TFAW_NS" value="30.0" />
<parameter name="MEM_TINIT_US" value="500" />
<parameter name="MEM_TMRD_CK" value="4" />
<parameter name="MEM_TRAS_NS" value="35.0" />
<parameter name="MEM_TRCD_NS" value="13.75" />
<parameter name="MEM_TREFI_US" value="7.8" />
<parameter name="MEM_TRFC_NS" value="110.0" />
<parameter name="MEM_TRP_NS" value="13.75" />
<parameter name="MEM_TRRD_NS" value="6.0" />
<parameter name="MEM_TRTP_NS" value="7.5" />
<parameter name="MEM_TWR_NS" value="15.0" />
<parameter name="MEM_TWTR" value="6" />
<parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
<parameter name="MEM_VENDOR" value="Micron" />
<parameter name="MEM_VERBOSE" value="true" />
<parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
<parameter name="MEM_WTCL" value="8" />
<parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
<parameter name="MULTICAST_EN" value="false" />
<parameter name="NEXTGEN" value="true" />
<parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
<parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
<parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
<parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
<parameter name="NUM_OF_PORTS" value="1" />
<parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
<parameter name="OCT_SHARING_MODE" value="None" />
<parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
<parameter name="PACKAGE_DESKEW" value="false" />
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
<parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
<parameter name="PHY_CSR_ENABLED" value="false" />
<parameter name="PHY_ONLY" value="false" />
<parameter name="PINGPONGPHY_EN" value="false" />
<parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_CLK_PARAM_VALID" value="false" />
<parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_LOCATION" value="Top_Bottom" />
<parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_SHARING_MODE" value="None" />
<parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="POWER_OF_TWO_BUS" value="false" />
<parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
<parameter name="RATE" value="Quarter" />
<parameter name="RDIMM_CONFIG" value="0" />
<parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
<parameter name="READ_FIFO_SIZE" value="8" />
<parameter name="REFRESH_BURST_VALIDATION" value="false" />
<parameter name="REFRESH_INTERVAL" value="15000" />
<parameter name="REF_CLK_FREQ" value="100.0" />
<parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
<parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
<parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
<parameter name="SEQUENCER_TYPE" value="NIOS" />
<parameter name="SEQ_MODE" value="0" />
<parameter name="SKIP_MEM_INIT" value="true" />
<parameter name="SOPC_COMPAT_RESET" value="false" />
<parameter name="SPEED_GRADE" value="3" />
<parameter name="STARVE_LIMIT" value="10" />
<parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
<parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
<parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
<parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
<parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
<parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
<parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
<parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
<parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
<parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
<parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
<parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
<parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
<parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
<parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
<parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
<parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
<parameter name="TIMING_BOARD_TDH" value="0.0" />
<parameter name="TIMING_BOARD_TDS" value="0.0" />
<parameter name="TIMING_BOARD_TIH" value="0.0" />
<parameter name="TIMING_BOARD_TIS" value="0.0" />
<parameter name="TIMING_TDH" value="45" />
<parameter name="TIMING_TDQSCK" value="255" />
<parameter name="TIMING_TDQSCKDL" value="1200" />
<parameter name="TIMING_TDQSCKDM" value="900" />
<parameter name="TIMING_TDQSCKDS" value="450" />
<parameter name="TIMING_TDQSQ" value="100" />
<parameter name="TIMING_TDQSS" value="0.27" />
<parameter name="TIMING_TDS" value="10" />
<parameter name="TIMING_TDSH" value="0.18" />
<parameter name="TIMING_TDSS" value="0.18" />
<parameter name="TIMING_TIH" value="120" />
<parameter name="TIMING_TIS" value="170" />
<parameter name="TIMING_TQH" value="0.38" />
<parameter name="TIMING_TQSH" value="0.4" />
<parameter name="TRACKING_ERROR_TEST" value="false" />
<parameter name="TRACKING_WATCH_TEST" value="false" />
<parameter name="TREFI" value="35100" />
<parameter name="TRFC" value="350" />
<parameter name="USER_DEBUG_LEVEL" value="1" />
<parameter name="USE_AXI_ADAPTOR" value="false" />
<parameter name="USE_FAKE_PHY" value="false" />
<parameter name="USE_MEM_CLK_FREQ" value="false" />
<parameter name="USE_MM_ADAPTOR" value="true" />
<parameter name="USE_SEQUENCER_BFM" value="false" />
<parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
<parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
</module>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<module name="sys_ethernet" kind="altera_eth_tse" version="15.1" enabled="1">
a5gt- base system
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<parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
<parameter name="core_variation" value="MAC_ONLY" />
<parameter name="deviceFamilyName" value="Arria V" />
<parameter name="eg_addr" value="11" />
<parameter name="ena_hash" value="false" />
<parameter name="enable_alt_reconfig" value="false" />
<parameter name="enable_ecc" value="false" />
<parameter name="enable_ena" value="32" />
<parameter name="enable_gmii_loopback" value="false" />
<parameter name="enable_hd_logic" value="true" />
<parameter name="enable_mac_flow_ctrl" value="true" />
<parameter name="enable_mac_vlan" value="false" />
<parameter name="enable_magic_detect" value="true" />
<parameter name="enable_ptp_1step" value="false" />
<parameter name="enable_sgmii" value="false" />
<parameter name="enable_shift16" value="true" />
<parameter name="enable_sup_addr" value="false" />
<parameter name="enable_timestamping" value="false" />
<parameter name="enable_use_internal_fifo" value="true" />
<parameter name="export_pwrdn" value="false" />
<parameter name="ext_stat_cnt_ena" value="false" />
<parameter name="ifGMII" value="RGMII" />
<parameter name="ing_addr" value="11" />
<parameter name="max_channels" value="1" />
<parameter name="mdio_clk_div" value="30" />
<parameter name="nf_phyip_rcfg_enable" value="false" />
<parameter name="phy_identifier" value="0" />
<parameter name="phyip_en_synce_support" value="false" />
<parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
<parameter name="phyip_pll_type" value="CMU" />
<parameter name="phyip_pma_bonding_mode" value="x1" />
<parameter name="starting_channel_number" value="0" />
<parameter name="stat_cnt_ena" value="true" />
<parameter name="transceiver_type" value="NONE" />
<parameter name="tstamp_fp_width" value="4" />
<parameter name="useMDIO" value="true" />
<parameter name="use_mac_clken" value="false" />
<parameter name="use_misc_ports" value="true" />
</module>
<module
name="sys_ethernet_dma_rx"
kind="altera_msgdma"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
enabled="1">
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
<parameter
name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
value="AddressWidth = -1" />
<parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
<parameter
name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
value="AddressWidth = -1" />
a5gt- base system
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<parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
<parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
<parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
a5gt- base system
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<parameter name="BURST_ENABLE" value="1" />
<parameter name="BURST_WRAPPING_SUPPORT" value="0" />
<parameter name="CHANNEL_ENABLE" value="0" />
<parameter name="CHANNEL_WIDTH" value="8" />
<parameter name="DATA_FIFO_DEPTH" value="256" />
<parameter name="DATA_WIDTH" value="64" />
<parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
<parameter name="ENHANCED_FEATURES" value="1" />
<parameter name="ERROR_ENABLE" value="1" />
<parameter name="ERROR_WIDTH" value="6" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="FIX_ADDRESS_WIDTH" value="32" />
a5gt- base system
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<parameter name="MAX_BURST_COUNT" value="64" />
<parameter name="MAX_BYTE" value="2048" />
<parameter name="MAX_STRIDE" value="1" />
<parameter name="MODE" value="2" />
<parameter name="PACKET_ENABLE" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="PREFETCHER_DATA_WIDTH" value="32" />
<parameter name="PREFETCHER_ENABLE" value="0" />
<parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
<parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
a5gt- base system
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<parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
<parameter name="RESPONSE_PORT" value="0" />
<parameter name="STRIDE_ENABLE" value="0" />
<parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
a5gt- base system
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</module>
<module
name="sys_ethernet_dma_tx"
kind="altera_msgdma"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
enabled="1">
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
<parameter
name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
value="AddressWidth = -1" />
<parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
<parameter
name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
value="AddressWidth = -1" />
a5gt- base system
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<parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
a5gt- base system
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<parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
<parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
<parameter name="BURST_ENABLE" value="1" />
<parameter name="BURST_WRAPPING_SUPPORT" value="0" />
<parameter name="CHANNEL_ENABLE" value="0" />
<parameter name="CHANNEL_WIDTH" value="8" />
<parameter name="DATA_FIFO_DEPTH" value="256" />
<parameter name="DATA_WIDTH" value="64" />
<parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
<parameter name="ENHANCED_FEATURES" value="1" />
<parameter name="ERROR_ENABLE" value="1" />
<parameter name="ERROR_WIDTH" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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<parameter name="FIX_ADDRESS_WIDTH" value="32" />
a5gt- base system
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<parameter name="MAX_BURST_COUNT" value="64" />
<parameter name="MAX_BYTE" value="2048" />
<parameter name="MAX_STRIDE" value="1" />
<parameter name="MODE" value="1" />
<parameter name="PACKET_ENABLE" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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<parameter name="PREFETCHER_DATA_WIDTH" value="32" />
<parameter name="PREFETCHER_ENABLE" value="0" />
<parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
<parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
a5gt- base system
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<parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
<parameter name="RESPONSE_PORT" value="2" />
<parameter name="STRIDE_ENABLE" value="0" />
<parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
a5gt- base system
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</module>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<module name="sys_gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
a5gt- base system
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<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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<parameter name="clockRate" value="100000000" />
a5gt- base system
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<parameter name="direction" value="InOut" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="true" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="32" />
</module>
<module
name="sys_gpio_bd"
kind="altera_avalon_pio"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
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enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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<parameter name="clockRate" value="100000000" />
a5gt- base system
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<parameter name="direction" value="InOut" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="true" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="32" />
</module>
<module
name="sys_id"
kind="altera_avalon_sysid_qsys"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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version="15.1"
a5gt- base system
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enabled="1">
<parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
<parameter name="id" value="0" />
</module>
<module
name="sys_int_mem"
kind="altera_avalon_onchip_memory2"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
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enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
<parameter name="blockType" value="AUTO" />
<parameter name="copyInitFile" value="false" />
<parameter name="dataWidth" value="32" />
<parameter name="deviceFamily" value="Arria V" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT
<parameter name="dualPort" value="true" />
a5gt- base system
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<parameter name="ecc_enabled" value="false" />
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="instanceID" value="NONE" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
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<parameter name="memorySize" value="786432" />
a5gt- base system
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<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="singleClockOperation" value="false" />
<parameter name="slave1Latency" value="1" />
<parameter name="slave2Latency" value="1" />
<parameter name="useNonDefaultInitFile" value="false" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<module name="sys_intr" kind="altera_irq_bridge" version="15.1" enabled="1">
<parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
<parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
<parameter name="IRQ_N" value="0" />
<parameter name="IRQ_WIDTH" value="8" />
</module>
<module
name="sys_mem_interconnect"
kind="altera_avalon_mm_bridge"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
enabled="1">
<parameter name="ADDRESS_UNITS" value="SYMBOLS" />
<parameter name="ADDRESS_WIDTH" value="29" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="DATA_WIDTH" value="256" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="LINEWRAPBURSTS" value="0" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="MAX_BURST_SIZE" value="64" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="MAX_PENDING_RESPONSES" value="4" />
<parameter name="PIPELINE_COMMAND" value="1" />
<parameter name="PIPELINE_RESPONSE" value="1" />
<parameter name="SYMBOL_WIDTH" value="8" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="SYSINFO_ADDR_WIDTH" value="28" />
<parameter name="USE_AUTO_ADDRESS_WIDTH" value="1" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="USE_RESPONSE" value="0" />
</module>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<module name="sys_pll" kind="altera_pll" version="15.1" enabled="1">
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="debug_print_output" value="false" />
<parameter name="debug_use_rbc_taf_method" value="false" />
<parameter name="device" value="5AGTFD7K3F40I3" />
<parameter name="device_family" value="Arria V" />
<parameter name="gui_active_clk" value="false" />
<parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency1" value="166.666666 MHz" />
<parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
<parameter name="gui_actual_phase_shift0" value="0" />
<parameter name="gui_actual_phase_shift1" value="0" />
<parameter name="gui_actual_phase_shift10" value="0" />
<parameter name="gui_actual_phase_shift11" value="0" />
<parameter name="gui_actual_phase_shift12" value="0" />
<parameter name="gui_actual_phase_shift13" value="0" />
<parameter name="gui_actual_phase_shift14" value="0" />
<parameter name="gui_actual_phase_shift15" value="0" />
<parameter name="gui_actual_phase_shift16" value="0" />
<parameter name="gui_actual_phase_shift17" value="0" />
<parameter name="gui_actual_phase_shift2" value="0" />
<parameter name="gui_actual_phase_shift3" value="0" />
<parameter name="gui_actual_phase_shift4" value="0" />
<parameter name="gui_actual_phase_shift5" value="0" />
<parameter name="gui_actual_phase_shift6" value="0" />
<parameter name="gui_actual_phase_shift7" value="0" />
<parameter name="gui_actual_phase_shift8" value="0" />
<parameter name="gui_actual_phase_shift9" value="0" />
<parameter name="gui_cascade_counter0" value="false" />
<parameter name="gui_cascade_counter1" value="false" />
<parameter name="gui_cascade_counter10" value="false" />
<parameter name="gui_cascade_counter11" value="false" />
<parameter name="gui_cascade_counter12" value="false" />
<parameter name="gui_cascade_counter13" value="false" />
<parameter name="gui_cascade_counter14" value="false" />
<parameter name="gui_cascade_counter15" value="false" />
<parameter name="gui_cascade_counter16" value="false" />
<parameter name="gui_cascade_counter17" value="false" />
<parameter name="gui_cascade_counter2" value="false" />
<parameter name="gui_cascade_counter3" value="false" />
<parameter name="gui_cascade_counter4" value="false" />
<parameter name="gui_cascade_counter5" value="false" />
<parameter name="gui_cascade_counter6" value="false" />
<parameter name="gui_cascade_counter7" value="false" />
<parameter name="gui_cascade_counter8" value="false" />
<parameter name="gui_cascade_counter9" value="false" />
<parameter name="gui_cascade_outclk_index" value="0" />
<parameter name="gui_channel_spacing" value="0.0" />
<parameter name="gui_clk_bad" value="false" />
<parameter name="gui_device_speed_grade" value="2" />
<parameter name="gui_divide_factor_c0" value="1" />
<parameter name="gui_divide_factor_c1" value="1" />
<parameter name="gui_divide_factor_c10" value="1" />
<parameter name="gui_divide_factor_c11" value="1" />
<parameter name="gui_divide_factor_c12" value="1" />
<parameter name="gui_divide_factor_c13" value="1" />
<parameter name="gui_divide_factor_c14" value="1" />
<parameter name="gui_divide_factor_c15" value="1" />
<parameter name="gui_divide_factor_c16" value="1" />
<parameter name="gui_divide_factor_c17" value="1" />
<parameter name="gui_divide_factor_c2" value="1" />
<parameter name="gui_divide_factor_c3" value="1" />
<parameter name="gui_divide_factor_c4" value="1" />
<parameter name="gui_divide_factor_c5" value="1" />
<parameter name="gui_divide_factor_c6" value="1" />
<parameter name="gui_divide_factor_c7" value="1" />
<parameter name="gui_divide_factor_c8" value="1" />
<parameter name="gui_divide_factor_c9" value="1" />
<parameter name="gui_divide_factor_n" value="1" />
<parameter name="gui_dps_cntr" value="C0" />
<parameter name="gui_dps_dir" value="Positive" />
<parameter name="gui_dps_num" value="1" />
<parameter name="gui_dsm_out_sel" value="1st_order" />
<parameter name="gui_duty_cycle0" value="50" />
<parameter name="gui_duty_cycle1" value="50" />
<parameter name="gui_duty_cycle10" value="50" />
<parameter name="gui_duty_cycle11" value="50" />
<parameter name="gui_duty_cycle12" value="50" />
<parameter name="gui_duty_cycle13" value="50" />
<parameter name="gui_duty_cycle14" value="50" />
<parameter name="gui_duty_cycle15" value="50" />
<parameter name="gui_duty_cycle16" value="50" />
<parameter name="gui_duty_cycle17" value="50" />
<parameter name="gui_duty_cycle2" value="50" />
<parameter name="gui_duty_cycle3" value="50" />
<parameter name="gui_duty_cycle4" value="50" />
<parameter name="gui_duty_cycle5" value="50" />
<parameter name="gui_duty_cycle6" value="50" />
<parameter name="gui_duty_cycle7" value="50" />
<parameter name="gui_duty_cycle8" value="50" />
<parameter name="gui_duty_cycle9" value="50" />
<parameter name="gui_en_adv_params" value="false" />
<parameter name="gui_en_dps_ports" value="false" />
<parameter name="gui_en_phout_ports" value="false" />
<parameter name="gui_en_reconf" value="false" />
<parameter name="gui_enable_cascade_in" value="false" />
<parameter name="gui_enable_cascade_out" value="false" />
<parameter name="gui_enable_mif_dps" value="false" />
<parameter name="gui_feedback_clock" value="Global Clock" />
<parameter name="gui_frac_multiply_factor" value="1" />
<parameter name="gui_fractional_cout" value="32" />
<parameter name="gui_mif_generate" value="false" />
<parameter name="gui_multiply_factor" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="gui_number_of_clocks" value="4" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="gui_operation_mode" value="direct" />
<parameter name="gui_output_clock_frequency0" value="125.0" />
<parameter name="gui_output_clock_frequency1" value="25.0" />
<parameter name="gui_output_clock_frequency10" value="100.0" />
<parameter name="gui_output_clock_frequency11" value="100.0" />
<parameter name="gui_output_clock_frequency12" value="100.0" />
<parameter name="gui_output_clock_frequency13" value="100.0" />
<parameter name="gui_output_clock_frequency14" value="100.0" />
<parameter name="gui_output_clock_frequency15" value="100.0" />
<parameter name="gui_output_clock_frequency16" value="100.0" />
<parameter name="gui_output_clock_frequency17" value="100.0" />
<parameter name="gui_output_clock_frequency2" value="2.5" />
<parameter name="gui_output_clock_frequency3" value="100.0" />
<parameter name="gui_output_clock_frequency4" value="100.0" />
<parameter name="gui_output_clock_frequency5" value="100.0" />
<parameter name="gui_output_clock_frequency6" value="100.0" />
<parameter name="gui_output_clock_frequency7" value="100.0" />
<parameter name="gui_output_clock_frequency8" value="100.0" />
<parameter name="gui_output_clock_frequency9" value="100.0" />
<parameter name="gui_phase_shift0" value="0" />
<parameter name="gui_phase_shift1" value="0" />
<parameter name="gui_phase_shift10" value="0" />
<parameter name="gui_phase_shift11" value="0" />
<parameter name="gui_phase_shift12" value="0" />
<parameter name="gui_phase_shift13" value="0" />
<parameter name="gui_phase_shift14" value="0" />
<parameter name="gui_phase_shift15" value="0" />
<parameter name="gui_phase_shift16" value="0" />
<parameter name="gui_phase_shift17" value="0" />
<parameter name="gui_phase_shift2" value="0" />
<parameter name="gui_phase_shift3" value="0" />
<parameter name="gui_phase_shift4" value="0" />
<parameter name="gui_phase_shift5" value="0" />
<parameter name="gui_phase_shift6" value="0" />
<parameter name="gui_phase_shift7" value="0" />
<parameter name="gui_phase_shift8" value="0" />
<parameter name="gui_phase_shift9" value="0" />
<parameter name="gui_phase_shift_deg0" value="0.0" />
<parameter name="gui_phase_shift_deg1" value="0.0" />
<parameter name="gui_phase_shift_deg10" value="0.0" />
<parameter name="gui_phase_shift_deg11" value="0.0" />
<parameter name="gui_phase_shift_deg12" value="0.0" />
<parameter name="gui_phase_shift_deg13" value="0.0" />
<parameter name="gui_phase_shift_deg14" value="0.0" />
<parameter name="gui_phase_shift_deg15" value="0.0" />
<parameter name="gui_phase_shift_deg16" value="0.0" />
<parameter name="gui_phase_shift_deg17" value="0.0" />
<parameter name="gui_phase_shift_deg2" value="0.0" />
<parameter name="gui_phase_shift_deg3" value="0.0" />
<parameter name="gui_phase_shift_deg4" value="0.0" />
<parameter name="gui_phase_shift_deg5" value="0.0" />
<parameter name="gui_phase_shift_deg6" value="0.0" />
<parameter name="gui_phase_shift_deg7" value="0.0" />
<parameter name="gui_phase_shift_deg8" value="0.0" />
<parameter name="gui_phase_shift_deg9" value="0.0" />
<parameter name="gui_phout_division" value="1" />
<parameter name="gui_pll_auto_reset" value="Off" />
<parameter name="gui_pll_bandwidth_preset" value="Auto" />
<parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
<parameter name="gui_pll_mode" value="Integer-N PLL" />
<parameter name="gui_ps_units0" value="ps" />
<parameter name="gui_ps_units1" value="ps" />
<parameter name="gui_ps_units10" value="ps" />
<parameter name="gui_ps_units11" value="ps" />
<parameter name="gui_ps_units12" value="ps" />
<parameter name="gui_ps_units13" value="ps" />
<parameter name="gui_ps_units14" value="ps" />
<parameter name="gui_ps_units15" value="ps" />
<parameter name="gui_ps_units16" value="ps" />
<parameter name="gui_ps_units17" value="ps" />
<parameter name="gui_ps_units2" value="ps" />
<parameter name="gui_ps_units3" value="ps" />
<parameter name="gui_ps_units4" value="ps" />
<parameter name="gui_ps_units5" value="ps" />
<parameter name="gui_ps_units6" value="ps" />
<parameter name="gui_ps_units7" value="ps" />
<parameter name="gui_ps_units8" value="ps" />
<parameter name="gui_ps_units9" value="ps" />
<parameter name="gui_refclk1_frequency" value="100.0" />
<parameter name="gui_refclk_switch" value="false" />
<parameter name="gui_reference_clock_frequency" value="100.0" />
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_locked" value="true" />
</module>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="ACTIVE_LOW_RESET" value="0" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="NUM_RESET_OUTPUTS" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="SYNCHRONOUS_EDGES" value="none" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="USE_RESET_REQUEST" value="0" />
</module>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<module name="sys_spi" kind="altera_avalon_spi" version="15.1" enabled="1">
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="avalonSpec" value="2.0" />
<parameter name="clockPhase" value="0" />
<parameter name="clockPolarity" value="0" />
<parameter name="dataWidth" value="8" />
<parameter name="disableAvalonFlowControl" value="false" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="inputClockRate" value="100000000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
<parameter name="insertSync" value="false" />
<parameter name="lsbOrderedFirst" value="false" />
<parameter name="masterSPI" value="true" />
<parameter name="numberOfSlaves" value="1" />
<parameter name="syncRegDepth" value="2" />
<parameter name="targetClockRate" value="128000" />
<parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
</module>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<module
name="sys_tcm_mem"
kind="altera_avalon_onchip_memory2"
version="15.1"
enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_sys_tcm_mem</parameter>
<parameter name="blockType" value="AUTO" />
<parameter name="copyInitFile" value="false" />
<parameter name="dataWidth" value="32" />
<parameter name="deviceFamily" value="Arria V" />
<parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT
<parameter name="dualPort" value="true" />
<parameter name="ecc_enabled" value="false" />
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="4096" />
<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="singleClockOperation" value="false" />
<parameter name="slave1Latency" value="1" />
<parameter name="slave2Latency" value="1" />
<parameter name="useNonDefaultInitFile" value="false" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
a5gt- base system
2015-07-22 19:04:59 +00:00
<module
name="sys_timer"
kind="altera_avalon_timer"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
enabled="1">
<parameter name="alwaysRun" value="false" />
<parameter name="counterSize" value="32" />
<parameter name="fixedPeriod" value="false" />
<parameter name="period" value="1" />
<parameter name="periodUnits" value="MSEC" />
<parameter name="resetOutput" value="false" />
<parameter name="snapshot" value="true" />
<parameter name="systemFrequency" value="100000000" />
<parameter name="timeoutPulseOutput" value="false" />
<parameter name="watchdogPulse" value="2" />
</module>
<module
name="sys_timer_2nd"
kind="altera_avalon_timer"
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
enabled="1">
<parameter name="alwaysRun" value="false" />
<parameter name="counterSize" value="32" />
<parameter name="fixedPeriod" value="false" />
<parameter name="period" value="1" />
<parameter name="periodUnits" value="MSEC" />
<parameter name="resetOutput" value="false" />
<parameter name="snapshot" value="true" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="systemFrequency" value="100000000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="timeoutPulseOutput" value="false" />
<parameter name="watchdogPulse" value="2" />
</module>
<module
name="sys_uart"
kind="altera_avalon_jtag_uart"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
enabled="1">
<parameter name="allowMultipleConnections" value="false" />
<parameter name="avalonSpec" value="2.0" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="clkFreq" value="100000000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="hubInstanceID" value="0" />
<parameter name="readBufferDepth" value="64" />
<parameter name="readIRQThreshold" value="8" />
<parameter name="simInputCharacterStream" value="" />
<parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
<parameter name="useRegistersForReadBuffer" value="false" />
<parameter name="useRegistersForWriteBuffer" value="false" />
<parameter name="useRelativePathForSimFile" value="false" />
<parameter name="writeBufferDepth" value="64" />
<parameter name="writeIRQThreshold" value="8" />
</module>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
end="sys_uart.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e4e0" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
end="sys_ddr3_cntrl.avl">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x0000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
end="sys_ethernet.control_port">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
end="sys_id.control_slave">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e4d8" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
end="sys_ethernet_dma_tx.csr">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e400" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
end="sys_ethernet_dma_rx.csr">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e440" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
end="sys_cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520d800" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
end="sys_ethernet_dma_rx.descriptor_slave">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e460" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
end="sys_ethernet_dma_tx.descriptor_slave">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e420" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
end="sys_ethernet_dma_rx.response">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e480" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_cpu_interconnect.s0">
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="arbitrationPriority" value="1" />
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
<parameter name="baseAddress" value="0x20000000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_int_mem.s1">
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x15000000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_gpio.s1">
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e4c0" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_timer.s1">
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e4a0" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_gpio_bd.s1">
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e520" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="sys_cpu.data_master"
end="sys_timer_2nd.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x1520e540" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.data_master"
end="sys_spi.spi_control_port">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520e500" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.instruction_master"
end="sys_ddr3_cntrl.avl">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x0000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.instruction_master"
end="sys_cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x1520d800" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.instruction_master"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
end="sys_int_mem.s2">
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x15000000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_mem_interconnect.m0"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_ddr3_cntrl.avl">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x0000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_ethernet_dma_tx.mm_read"
end="sys_ddr3_cntrl.avl">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x0000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_ethernet_dma_rx.mm_write"
end="sys_ddr3_cntrl.avl">
<parameter name="arbitrationPriority" value="1" />
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="sys_cpu.tightly_coupled_data_master_0"
end="sys_tcm_mem.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x1520c000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="sys_cpu.tightly_coupled_instruction_master_0"
end="sys_tcm_mem.s2">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x1520c000" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon_streaming"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_ethernet.receive"
end="sys_ethernet_dma_rx.st_sink" />
<connection
kind="avalon_streaming"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_ethernet_dma_tx.st_source"
end="sys_ethernet.transmit" />
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_ddr3_cntrl.afi_clk"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_mem_interconnect.clk" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_ddr3_cntrl.afi_clk"
end="mem_clk.in_clk" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_clk.out_clk"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
end="sys_ddr3_cntrl.pll_ref_clk" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_clk.out_clk"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
end="sys_pll.refclk" />
<connection kind="clock" version="15.1" start="sys_pll.outclk3" end="sys_cpu.clk" />
<connection
kind="clock"
version="15.1"
start="sys_pll.outclk3"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_timer.clk" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_pll.outclk3"
end="sys_timer_2nd.clk" />
<connection kind="clock" version="15.1" start="sys_pll.outclk3" end="sys_id.clk" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_pll.outclk3"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_gpio.clk" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_pll.outclk3"
end="sys_gpio_bd.clk" />
<connection kind="clock" version="15.1" start="sys_pll.outclk3" end="sys_spi.clk" />
<connection
kind="clock"
version="15.1"
start="sys_pll.outclk3"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_cpu_interconnect.clk" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_pll.outclk3"
end="sys_uart.clk" />
<connection
kind="clock"
version="15.1"
start="sys_pll.outclk3"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_intr.clk" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_pll.outclk3"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_int_mem.clk1" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_pll.outclk3"
end="sys_tcm_mem.clk1" />
<connection
kind="clock"
version="15.1"
start="sys_pll.outclk3"
end="sys_int_mem.clk2" />
<connection
kind="clock"
version="15.1"
start="sys_pll.outclk3"
end="sys_tcm_mem.clk2" />
<connection
kind="clock"
version="15.1"
start="sys_pll.outclk3"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_ethernet_dma_rx.clock" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_pll.outclk3"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_ethernet_dma_tx.clock" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_pll.outclk3"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_ethernet.control_port_clock_connection" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_pll.outclk3"
end="cpu_clk.in_clk" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_pll.outclk3"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_ethernet.receive_clock_connection" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="clock"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_pll.outclk3"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_ethernet.transmit_clock_connection" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_cpu.irq"
end="sys_ethernet_dma_rx.csr_irq">
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="irqNumber" value="3" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_cpu.irq"
end="sys_ethernet_dma_tx.csr_irq">
<parameter name="irqNumber" value="1" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_cpu.irq"
end="sys_uart.irq">
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="irqNumber" value="2" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_cpu.irq"
end="sys_timer.irq">
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="irqNumber" value="0" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<connection kind="interrupt" version="15.1" start="sys_cpu.irq" end="sys_spi.irq">
<parameter name="irqNumber" value="4" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_cpu.irq"
end="sys_gpio.irq">
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="irqNumber" value="6" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_cpu.irq"
end="sys_gpio_bd.irq">
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="irqNumber" value="5" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_cpu.irq"
end="sys_timer_2nd.irq">
<parameter name="irqNumber" value="7" />
</connection>
<connection
kind="interrupt"
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.irq"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_intr.sender0_irq">
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="irqNumber" value="15" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.irq"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_intr.sender1_irq">
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
<parameter name="irqNumber" value="8" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.irq"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_intr.sender2_irq">
<parameter name="irqNumber" value="9" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.irq"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_intr.sender3_irq">
<parameter name="irqNumber" value="10" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.irq"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_intr.sender4_irq">
<parameter name="irqNumber" value="11" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.irq"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_intr.sender5_irq">
<parameter name="irqNumber" value="12" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.irq"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_intr.sender6_irq">
<parameter name="irqNumber" value="13" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
kind="interrupt"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_cpu.irq"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_intr.sender7_irq">
<parameter name="irqNumber" value="14" />
a5gt- base system
2015-07-22 19:04:59 +00:00
</connection>
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_ddr3_cntrl.afi_reset"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="mem_rst.in_reset" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt- base system
2015-07-22 19:04:59 +00:00
start="sys_ddr3_cntrl.afi_reset"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
end="sys_mem_interconnect.reset" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_cpu.debug_reset_request"
end="sys_cpu.reset" />
<connection
kind="reset"
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
end="sys_intr.clk_reset" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_ddr3_cntrl.global_reset" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_rst.out_reset"
end="cpu_reset.in_reset" />
<connection
kind="reset"
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_pll.reset" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_cpu.reset" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_uart.reset" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_timer.reset" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_id.reset" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
end="sys_gpio_bd.reset" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_gpio.reset" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_spi.reset" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
end="sys_cpu_interconnect.reset" />
a5gt- base system
2015-07-22 19:04:59 +00:00
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_rst.out_reset"
end="sys_timer_2nd.reset" />
<connection
kind="reset"
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_int_mem.reset1" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
start="sys_rst.out_reset"
end="sys_tcm_mem.reset1" />
<connection
kind="reset"
version="15.1"
start="sys_rst.out_reset"
end="sys_int_mem.reset2" />
<connection
kind="reset"
version="15.1"
start="sys_rst.out_reset"
end="sys_tcm_mem.reset2" />
<connection
kind="reset"
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_ethernet.reset_connection" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_ethernet_dma_rx.reset_n" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_ethernet_dma_tx.reset_n" />
<connection
kind="reset"
fmcjesdadc1: Fixed project - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release
2016-02-19 12:09:57 +00:00
version="15.1"
a5gt-base: initial updates
2015-07-22 19:22:22 +00:00
start="sys_rst.out_reset"
a5gt- base system
2015-07-22 19:04:59 +00:00
end="sys_ddr3_cntrl.soft_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
</system>