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pluto_hdl_adi/projects/dac_fmc_ebz/zcu102/system_constr.xdc

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Add copyright and license to .xdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-10 08:38:46 +00:00
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the ZCU102 and ZC706 carrier boards. The project is called dac_fmc_ebz as the intention is to support all DAC FMC evaluation boards with this project since they are sufficiently similar to be supported by the same design. This project will successively extended to add support for more boards. The desired DAC device and JESD operation mode must be selected from the following file: ./common/config.tcl This design can support the following FMC boards which are all pin compatible: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD916x-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other boards use 8 lanes. This project assumes that the transceiver reference clock and SYSREF are provided via the clock distribution chip that is found on the ADxxxx-FMC-EBZ board. In terms of pin connections between the FPGA and the FMC board the AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ. The main differences are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this 5 txctrl signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * ZC706: 10.3125 Gbps * ZCU102: 15.4 Gbps (max AD9172 lanerate) * SPI and GPIOs to PMOD header support Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102 and zc706 carriers. This is can be used to control additional external hardware like a clock chip or an analog front-end. This is especially useful on FMC boards that do not feature a clock generator chip. The pin out is: PMOD 1: SPI clock PMOD 2: SPI chipselect PMOD 3: SPI MOSI PMOD 4: SPI MISO PMOD 7: GPIO 0 PMOD 8: GPIO 1 PMOD 9: GPIO 2 PMOD 10: GPIO 3 The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2018-06-15 11:50:34 +00:00
# DAC FMC signals
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p[0]] ; ## D08 FMC_HPC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66_AB4
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n[0]] ; ## D09 FMC_HPC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66_AC4
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p[1]] ; ## H08 FMC_HPC0_LA02_P IO_L23P_T3U_N8_66_V2
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n[1]] ; ## H09 FMC_HPC0_LA02_N IO_L23N_T3U_N9_66_V1
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_p] ; ## G06 FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66_Y4
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_n] ; ## G07 FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66_Y3
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18} [get_ports spi_csn_dac] ; ## H11 FMC_HPC0_LA04_N IO_L21N_T3L_N5_AD8N_66_AA1
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## D11 FMC_HPC0_LA05_P IO_L20P_T3L_N2_AD1P_66_AB3
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## H10 FMC_HPC0_LA04_P IO_L21P_T3L_N4_AD8P_66_AA2
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## G10 FMC_HPC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66_Y1
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## G09 FMC_HPC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66_Y2
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports spi_en] ; ## D12 FMC_HPC0_LA05_N IO_L20N_T3L_N3_AD1N_66_AC3
# For AD916(1,2,3,4)-FMC-EBZ
set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk2] ; ## D14 FMC_HPC_LA09_P IO_L10P_T1_11
# For AD9135-FMC-EBZ, AD9136-FMC-EBZ, AD9144-FMC-EBZ, AD9152-FMC-EBZ, AD9154-FMC-EBZ
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18} [get_ports dac_ctrl[0]] ; ## H13 FMC_HPC0_LA07_P IO_L18P_T2U_N10_AD2P_66_U5
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18} [get_ports dac_ctrl[3]] ; ## H14 FMC_HPC0_LA07_N IO_L18N_T2U_N11_AD2N_66_U4
# For AD9171-FMC-EBZ, AD9172-FMC-EBZ, AD9173-FMC-EBZ
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports dac_ctrl[1]] ; ## C10 FMC_HPC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66_AC2
set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18} [get_ports dac_ctrl[2]] ; ## C11 FMC_HPC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66_AC1
# For AD916(1,2,3,4)-FMC-EBZ
set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18} [get_ports dac_ctrl[4]] ; ## D15 FMC_HPC_LA09_P IO_L10N_T1_11
set_property -dict {PACKAGE_PIN G8} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC0_GBTCLK0_M2C_C_P MGTREFCLK0P_229_G8
set_property -dict {PACKAGE_PIN G7} [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC0_GBTCLK0_M2C_C_N MGTREFCLK0N_229_G7
dac_fmc_ebz_bd.tcl: Updated bd for multiple tx_ref_clk
2022-02-04 13:45:28 +00:00
set_property -dict {PACKAGE_PIN G3} [get_ports tx_data_n[7]] ; ## C03 FMC_HPC0_DP0_C2M_N MGTHTXN2_229_G3
set_property -dict {PACKAGE_PIN G4} [get_ports tx_data_p[7]] ; ## C02 FMC_HPC0_DP0_C2M_P MGTHTXP2_229_G4
set_property -dict {PACKAGE_PIN H5} [get_ports tx_data_n[6]] ; ## A23 FMC_HPC0_DP1_C2M_N MGTHTXN1_229_H5
set_property -dict {PACKAGE_PIN H6} [get_ports tx_data_p[6]] ; ## A22 FMC_HPC0_DP1_C2M_P MGTHTXP1_229_H6
set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[5]] ; ## A27 FMC_HPC0_DP2_C2M_N MGTHTXN3_229_F5
set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[5]] ; ## A26 FMC_HPC0_DP2_C2M_P MGTHTXP3_229_F6
set_property -dict {PACKAGE_PIN K5} [get_ports tx_data_n[4]] ; ## A31 FMC_HPC0_DP3_C2M_N MGTHTXN0_229_K5
set_property -dict {PACKAGE_PIN K6} [get_ports tx_data_p[4]] ; ## A30 FMC_HPC0_DP3_C2M_P MGTHTXP0_229_K6
set_property -dict {PACKAGE_PIN M6} [get_ports tx_data_p[2]] ; ## A34 FMC_HPC0_DP4_C2M_P MGTHTXP3_228_M6
set_property -dict {PACKAGE_PIN M5} [get_ports tx_data_n[2]] ; ## A35 FMC_HPC0_DP4_C2M_N MGTHTXN3_228_M5
set_property -dict {PACKAGE_PIN P6} [get_ports tx_data_p[0]] ; ## A38 FMC_HPC0_DP5_C2M_P MGTHTXP1_228_P6
set_property -dict {PACKAGE_PIN P5} [get_ports tx_data_n[0]] ; ## A39 FMC_HPC0_DP5_C2M_N MGTHTXN1_228_P5
set_property -dict {PACKAGE_PIN R4} [get_ports tx_data_p[1]] ; ## B36 FMC_HPC0_DP6_C2M_P MGTHTXP0_228_R4
set_property -dict {PACKAGE_PIN R3} [get_ports tx_data_n[1]] ; ## B37 FMC_HPC0_DP6_C2M_N MGTHTXN0_228_R3
set_property -dict {PACKAGE_PIN N4} [get_ports tx_data_p[3]] ; ## B32 FMC_HPC0_DP7_C2M_P MGTHTXP2_228_N4
set_property -dict {PACKAGE_PIN N3} [get_ports tx_data_n[3]] ; ## B33 FMC_HPC0_DP7_C2M_N MGTHTXN2_228_N3
dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the ZCU102 and ZC706 carrier boards. The project is called dac_fmc_ebz as the intention is to support all DAC FMC evaluation boards with this project since they are sufficiently similar to be supported by the same design. This project will successively extended to add support for more boards. The desired DAC device and JESD operation mode must be selected from the following file: ./common/config.tcl This design can support the following FMC boards which are all pin compatible: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD916x-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other boards use 8 lanes. This project assumes that the transceiver reference clock and SYSREF are provided via the clock distribution chip that is found on the ADxxxx-FMC-EBZ board. In terms of pin connections between the FPGA and the FMC board the AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ. The main differences are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this 5 txctrl signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * ZC706: 10.3125 Gbps * ZCU102: 15.4 Gbps (max AD9172 lanerate) * SPI and GPIOs to PMOD header support Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102 and zc706 carriers. This is can be used to control additional external hardware like a clock chip or an analog front-end. This is especially useful on FMC boards that do not feature a clock generator chip. The pin out is: PMOD 1: SPI clock PMOD 2: SPI chipselect PMOD 3: SPI MOSI PMOD 4: SPI MISO PMOD 7: GPIO 0 PMOD 8: GPIO 1 PMOD 9: GPIO 2 PMOD 10: GPIO 3 The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2018-06-15 11:50:34 +00:00
# PL PMOD 1 header
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports pmod_spi_clk] ; ## PMOD1_0 IO_L8N_HDGC_AD4N_47_D20
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports pmod_spi_csn] ; ## PMOD1_1 IO_L8P_HDGC_AD4P_47_E20
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports pmod_spi_mosi] ; ## PMOD1_2 IO_L7N_HDGC_AD5N_47_D22
set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33} [get_ports pmod_spi_miso] ; ## PMOD1_3 IO_L7P_HDGC_AD5P_47_E22
set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS33} [get_ports pmod_gpio[0]] ; ## PMOD1_4 IO_L6N_HDGC_AD6N_47_F20
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33} [get_ports pmod_gpio[1]] ; ## PMOD1_5 IO_L6P_HDGC_AD6P_47_G20
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS33} [get_ports pmod_gpio[2]] ; ## PMOD1_6 IO_L4N_AD8N_47_J20
set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS33} [get_ports pmod_gpio[3]] ; ## PMOD1_7 IO_L4P_AD8P_47_J19
# clocks
# Max lane rate of 15.4 Gbps
create_clock -name tx_ref_clk -period 2.597 [get_ports tx_ref_clk_p]
# Assumption is that REFCLK and SYSREF have similar propagation delay,
# and the SYSREF is a source synchronous Center-Aligned signal to REFCLK
set_input_delay -clock [get_clocks tx_ref_clk] \
[expr [get_property PERIOD [get_clocks tx_ref_clk]] / 2] \
[get_ports {tx_sysref_*}]