pluto_hdl_adi/projects/fmcomms2/zcu102/system_top.v

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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
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//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
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//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
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//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
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//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
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input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
output enable,
output txnrx,
output gpio_resetb,
output gpio_sync,
output gpio_en_agc,
output [ 3:0] gpio_ctl,
input [ 7:0] gpio_status,
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso
);
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// internal signals
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wire [94:0] gpio_i;
wire [94:0] gpio_o;
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wire [ 2:0] spi0_csn;
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// defaults
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assign gpio_resetb = gpio_o[46:46];
assign gpio_sync = gpio_o[45:45];
assign gpio_en_agc = gpio_o[44:44];
assign gpio_ctl = gpio_o[43:40];
assign gpio_bd_o = gpio_o[20:13];
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assign gpio_i[94:40] = gpio_o[94:40];
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assign gpio_i[39:32] = gpio_status;
assign gpio_i[31:13] = gpio_o[31:13];
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assign gpio_i[12: 0] = gpio_bd_i;
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assign spi_csn = spi0_csn[0];
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// instantiations
system_wrapper i_system_wrapper (
.enable (enable),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (),
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.rx_clk_in_n (rx_clk_in_n),
.rx_clk_in_p (rx_clk_in_p),
.rx_data_in_n (rx_data_in_n),
.rx_data_in_p (rx_data_in_p),
.rx_frame_in_n (rx_frame_in_n),
.rx_frame_in_p (rx_frame_in_p),
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.spi0_csn (spi0_csn),
.spi0_miso (spi_miso),
.spi0_mosi (spi_mosi),
.spi0_sclk (spi_clk),
.spi1_csn (),
.spi1_miso (1'b0),
.spi1_mosi (),
.spi1_sclk (),
.tdd_sync_i (1'b0),
.tdd_sync_o (),
.tdd_sync_t (),
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.tx_clk_out_n (tx_clk_out_n),
.tx_clk_out_p (tx_clk_out_p),
.tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx),
.up_enable (gpio_o[47]),
.up_txnrx (gpio_o[48]));
endmodule