332 lines
11 KiB
Coq
332 lines
11 KiB
Coq
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// -------------------------------------------------------------
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//
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// Module: fir_decim
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// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
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// Generated on: 2016-07-05 15:45:22
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// -------------------------------------------------------------
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// -------------------------------------------------------------
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// HDL Code Generation Options:
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//
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// FIRAdderStyle: tree
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// OptimizeForHDL: on
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// EDAScriptGeneration: off
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// AddPipelineRegisters: on
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// Name: fir_decim
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// TargetLanguage: Verilog
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// TestBenchName: fo_copy_tb
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// TestBenchStimulus: step ramp chirp noise
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// GenerateHDLTestBench: off
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// -------------------------------------------------------------
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// HDL Implementation : Fully parallel
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// Multipliers : 6
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// Folding Factor : 1
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// -------------------------------------------------------------
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// Filter Settings:
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//
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// Discrete-Time FIR Multirate Filter (real)
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// -----------------------------------------
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// Filter Structure : Direct-Form FIR Polyphase Decimator
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// Decimation Factor : 2
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// Polyphase Length : 3
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// Filter Length : 6
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// Stable : Yes
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// Linear Phase : Yes (Type 2)
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//
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// Arithmetic : fixed
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// Numerator : s12,11 -> [-1 1)
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// -------------------------------------------------------------
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`timescale 1 ns / 1 ns
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module fir_decim
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(
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clk,
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clk_enable,
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reset,
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filter_in,
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filter_out,
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ce_out
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);
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input clk;
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input clk_enable;
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input reset;
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input signed [11:0] filter_in; //sfix12_En11
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output signed [25:0] filter_out; //sfix26_En22
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output ce_out;
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////////////////////////////////////////////////////////////////
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//Module Architecture: fir_decim
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////////////////////////////////////////////////////////////////
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// Local Functions
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// Type Definitions
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// Constants
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parameter signed [11:0] coeffphase1_1 = 12'b000011010101; //sfix12_En11
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parameter signed [11:0] coeffphase1_2 = 12'b011011110010; //sfix12_En11
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parameter signed [11:0] coeffphase1_3 = 12'b110000111110; //sfix12_En11
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parameter signed [11:0] coeffphase2_1 = 12'b110000111110; //sfix12_En11
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parameter signed [11:0] coeffphase2_2 = 12'b011011110010; //sfix12_En11
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parameter signed [11:0] coeffphase2_3 = 12'b000011010101; //sfix12_En11
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// Signals
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reg [1:0] ring_count; // ufix2
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wire phase_0; // boolean
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wire phase_1; // boolean
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reg ce_out_reg; // boolean
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reg signed [11:0] input_register; // sfix12_En11
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reg signed [11:0] input_pipeline_phase0 [0:1] ; // sfix12_En11
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reg signed [11:0] input_pipeline_phase1 [0:2] ; // sfix12_En11
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wire signed [23:0] product_phase0_1; // sfix24_En22
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wire signed [23:0] product_phase0_2; // sfix24_En22
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wire signed [23:0] product_phase0_3; // sfix24_En22
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wire signed [23:0] product_phase1_1; // sfix24_En22
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wire signed [23:0] product_phase1_2; // sfix24_En22
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wire signed [23:0] product_phase1_3; // sfix24_En22
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reg signed [23:0] product_pipeline_phase0_1; // sfix24_En22
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reg signed [23:0] product_pipeline_phase0_2; // sfix24_En22
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reg signed [23:0] product_pipeline_phase0_3; // sfix24_En22
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reg signed [23:0] product_pipeline_phase1_1; // sfix24_En22
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reg signed [23:0] product_pipeline_phase1_2; // sfix24_En22
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reg signed [23:0] product_pipeline_phase1_3; // sfix24_En22
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wire signed [25:0] sumvector1 [0:2] ; // sfix26_En22
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wire signed [23:0] add_signext; // sfix24_En22
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wire signed [23:0] add_signext_1; // sfix24_En22
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wire signed [24:0] add_temp; // sfix25_En22
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wire signed [23:0] add_signext_2; // sfix24_En22
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wire signed [23:0] add_signext_3; // sfix24_En22
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wire signed [24:0] add_temp_1; // sfix25_En22
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wire signed [23:0] add_signext_4; // sfix24_En22
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wire signed [23:0] add_signext_5; // sfix24_En22
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wire signed [24:0] add_temp_2; // sfix25_En22
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reg signed [25:0] sumdelay_pipeline1 [0:2] ; // sfix26_En22
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wire signed [25:0] sumvector2 [0:1] ; // sfix26_En22
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wire signed [25:0] add_signext_6; // sfix26_En22
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wire signed [25:0] add_signext_7; // sfix26_En22
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wire signed [26:0] add_temp_3; // sfix27_En22
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reg signed [25:0] sumdelay_pipeline2 [0:1] ; // sfix26_En22
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wire signed [25:0] sum3; // sfix26_En22
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wire signed [25:0] add_signext_8; // sfix26_En22
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wire signed [25:0] add_signext_9; // sfix26_En22
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wire signed [26:0] add_temp_4; // sfix27_En22
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reg ce_delayline1; // boolean
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reg ce_delayline2; // boolean
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reg ce_delayline3; // boolean
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reg ce_delayline4; // boolean
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reg ce_delayline5; // boolean
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reg ce_delayline6; // boolean
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reg ce_delayline7; // boolean
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reg ce_delayline8; // boolean
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wire ce_gated; // boolean
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reg signed [25:0] output_register; // sfix26_En22
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// Block Statements
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always @ (posedge clk or posedge reset)
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begin: ce_output
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if (reset == 1'b1) begin
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ring_count <= 1;
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end
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else begin
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if (clk_enable == 1'b1) begin
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ring_count <= {ring_count[0], ring_count[1]};
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end
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end
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end // ce_output
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assign phase_0 = ring_count[0] && clk_enable;
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assign phase_1 = ring_count[1] && clk_enable;
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// ------------------ CE Output Register ------------------
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always @ (posedge clk or posedge reset)
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begin: ce_output_register
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if (reset == 1'b1) begin
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ce_out_reg <= 1'b0;
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end
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else begin
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ce_out_reg <= phase_1;
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end
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end // ce_output_register
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always @ (posedge clk or posedge reset)
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begin: input_reg_process
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if (reset == 1'b1) begin
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input_register <= 0;
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end
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else begin
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if (clk_enable == 1'b1) begin
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input_register <= filter_in;
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end
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end
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end // input_reg_process
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always @( posedge clk or posedge reset)
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begin: Delay_Pipeline_Phase0_process
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if (reset == 1'b1) begin
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input_pipeline_phase0[0] <= 0;
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input_pipeline_phase0[1] <= 0;
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end
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else begin
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if (phase_1 == 1'b1) begin
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input_pipeline_phase0[0] <= input_register;
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input_pipeline_phase0[1] <= input_pipeline_phase0[0];
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end
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end
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end // Delay_Pipeline_Phase0_process
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always @( posedge clk or posedge reset)
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begin: Delay_Pipeline_Phase1_process
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if (reset == 1'b1) begin
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input_pipeline_phase1[0] <= 0;
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input_pipeline_phase1[1] <= 0;
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input_pipeline_phase1[2] <= 0;
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end
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else begin
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if (phase_0 == 1'b1) begin
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input_pipeline_phase1[0] <= input_register;
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input_pipeline_phase1[1] <= input_pipeline_phase1[0];
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input_pipeline_phase1[2] <= input_pipeline_phase1[1];
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end
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end
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end // Delay_Pipeline_Phase1_process
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assign product_phase0_1 = input_register * coeffphase1_1;
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assign product_phase0_2 = input_pipeline_phase0[0] * coeffphase1_2;
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assign product_phase0_3 = input_pipeline_phase0[1] * coeffphase1_3;
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assign product_phase1_1 = input_pipeline_phase1[0] * coeffphase2_1;
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assign product_phase1_2 = input_pipeline_phase1[1] * coeffphase2_2;
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assign product_phase1_3 = input_pipeline_phase1[2] * coeffphase2_3;
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always @ (posedge clk or posedge reset)
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begin: product_pipeline_process1
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if (reset == 1'b1) begin
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product_pipeline_phase0_1 <= 0;
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product_pipeline_phase1_1 <= 0;
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product_pipeline_phase0_2 <= 0;
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product_pipeline_phase1_2 <= 0;
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product_pipeline_phase0_3 <= 0;
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product_pipeline_phase1_3 <= 0;
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end
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else begin
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if (phase_1 == 1'b1) begin
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product_pipeline_phase0_1 <= product_phase0_1;
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product_pipeline_phase1_1 <= product_phase1_1;
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product_pipeline_phase0_2 <= product_phase0_2;
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product_pipeline_phase1_2 <= product_phase1_2;
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product_pipeline_phase0_3 <= product_phase0_3;
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product_pipeline_phase1_3 <= product_phase1_3;
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end
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end
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end // product_pipeline_process1
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assign add_signext = product_pipeline_phase1_1;
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assign add_signext_1 = product_pipeline_phase1_2;
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assign add_temp = add_signext + add_signext_1;
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assign sumvector1[0] = $signed({{1{add_temp[24]}}, add_temp});
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assign add_signext_2 = product_pipeline_phase1_3;
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assign add_signext_3 = product_pipeline_phase0_1;
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assign add_temp_1 = add_signext_2 + add_signext_3;
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assign sumvector1[1] = $signed({{1{add_temp_1[24]}}, add_temp_1});
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assign add_signext_4 = product_pipeline_phase0_2;
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assign add_signext_5 = product_pipeline_phase0_3;
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assign add_temp_2 = add_signext_4 + add_signext_5;
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assign sumvector1[2] = $signed({{1{add_temp_2[24]}}, add_temp_2});
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always @ (posedge clk or posedge reset)
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begin: sumdelay_pipeline_process1
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if (reset == 1'b1) begin
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sumdelay_pipeline1[0] <= 0;
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sumdelay_pipeline1[1] <= 0;
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sumdelay_pipeline1[2] <= 0;
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end
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else begin
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if (phase_1 == 1'b1) begin
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sumdelay_pipeline1[0] <= sumvector1[0];
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sumdelay_pipeline1[1] <= sumvector1[1];
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sumdelay_pipeline1[2] <= sumvector1[2];
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end
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end
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end // sumdelay_pipeline_process1
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assign add_signext_6 = sumdelay_pipeline1[0];
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assign add_signext_7 = sumdelay_pipeline1[1];
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assign add_temp_3 = add_signext_6 + add_signext_7;
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assign sumvector2[0] = add_temp_3[25:0];
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assign sumvector2[1] = sumdelay_pipeline1[2];
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always @ (posedge clk or posedge reset)
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begin: sumdelay_pipeline_process2
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if (reset == 1'b1) begin
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sumdelay_pipeline2[0] <= 0;
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sumdelay_pipeline2[1] <= 0;
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end
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else begin
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if (phase_1 == 1'b1) begin
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sumdelay_pipeline2[0] <= sumvector2[0];
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sumdelay_pipeline2[1] <= sumvector2[1];
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end
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end
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end // sumdelay_pipeline_process2
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assign add_signext_8 = sumdelay_pipeline2[0];
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assign add_signext_9 = sumdelay_pipeline2[1];
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assign add_temp_4 = add_signext_8 + add_signext_9;
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assign sum3 = add_temp_4[25:0];
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always @ (posedge clk or posedge reset)
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begin: ce_delay
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if (reset == 1'b1) begin
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ce_delayline1 <= 1'b0;
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ce_delayline2 <= 1'b0;
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ce_delayline3 <= 1'b0;
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ce_delayline4 <= 1'b0;
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ce_delayline5 <= 1'b0;
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ce_delayline6 <= 1'b0;
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ce_delayline7 <= 1'b0;
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ce_delayline8 <= 1'b0;
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end
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else begin
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if (clk_enable == 1'b1) begin
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ce_delayline1 <= clk_enable;
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ce_delayline2 <= ce_delayline1;
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ce_delayline3 <= ce_delayline2;
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ce_delayline4 <= ce_delayline3;
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ce_delayline5 <= ce_delayline4;
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ce_delayline6 <= ce_delayline5;
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ce_delayline7 <= ce_delayline6;
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ce_delayline8 <= ce_delayline7;
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end
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end
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end // ce_delay
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assign ce_gated = ce_delayline8 & ce_out_reg;
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always @ (posedge clk or posedge reset)
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begin: output_register_process
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if (reset == 1'b1) begin
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output_register <= 0;
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end
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else begin
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if (phase_1 == 1'b1) begin
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output_register <= sum3;
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end
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end
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end // output_register_process
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// Assignment Statements
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assign ce_out = ce_gated;
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assign filter_out = output_register;
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endmodule // fir_decim
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