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pluto_hdl_adi/projects/ad_fmclidar1_ebz/zc706/system_bd.tcl

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ad_fmclidar1_ebz: Initial commit This commit was created by squashing the following commits, these messages were kept just for sake of history: ad9694_500ebz: Mirror the SPI interface to FMCB ad9694_500ebz: Set transceiver reference clock to 250 ad9694_500ebz: Allow to configure number of lanes, number of converters and sample rate axi_ad9694: Fix number of lanes, it must be 2 ad9694_500ebz: Update the mirrored spi pin assignments ad9694_500ebz: Gate SPI MISO signals based on chip-select ad9694_500ebz: Set channel pack sample width ad9694_500ebz: Change reference clock location ad9694_500ebz: Remove transceiver memory map arbitration ad9694_500ebz: Ensure ADC FIFO DMA_DATA_WIDTH is not larger ADC_DATA_WIDTH ad9694_500ebz: Adjust breakout board pin locations ad_fmclidar1_ebz: Rename the ad9694_500ebz project ad_fmclidar1_ebz: Fix lane mapping ad_fmclidar1_ebz: Delete deprecated files ad_fmclidar1_ebz: Integrate the axi_laser_driver into the design ad_fmclidar1_ebz: OTW is an active low signal ad_fmclidar1_ebz: zc706: Fix iic_dac signals assignment ad_fmclidar1_ebz: Switch to util_adcfifo ad_fmclidar1_ebz: Enable synced capture for the fifo ad_fmclidar1_ebz/zc706: Enable CAPTURE_TILL_FULL ad_fmclidar1_ebz/zc706: Reduce FIFO size to 2kB ad_fmclidar1_ebz: Laser driver runs on ADC's core clock ad_fmclidar1_ebz_bd: Delete the FIFO instance Because the DMA transfers are going to be relatively small (< 2kbyte), the DMA can handle the data rate, even when the frequency of the laser driver pulse is set to its maximum value. (200 kHz) The synchronization will be done by connecting the generated pulse to the DMA's SYNC input. Although, to support 2 or 1 channel scenarios, we need to use the util_axis_syncgen module to make sure that the DMA catches the pulse, in cases when the pulse width is too narrow. (SYNC is captures when valid and ready is asserted) Also we have to reset the cpack IP before each pulse, to keep the DMA buffer's relative starting point in time fixed, when only 2 or 1 channel is active.
2017-11-10 13:22:16 +00:00
# Configurable parameters
set SAMPLE_RATE_MHZ 1000.0
set NUM_OF_CHANNELS 4 ; # M
set SAMPLES_PER_FRAME 1 ; # S
set NUM_OF_LANES 4 ; # L
set ADC_RESOLUTION 8 ; # N & NP
# Auto-computed parameters
set CHANNEL_DATA_WIDTH [expr 32 * $NUM_OF_LANES / $NUM_OF_CHANNELS]
set ADC_DATA_WIDTH [expr $CHANNEL_DATA_WIDTH * $NUM_OF_CHANNELS]
ad_fmclidar1_ebz: Add a dummy ADC channel with TIA channel info Software has to know which TIA channel was used for a particular capture. Define an additional dummy ADC channel which will provide this information. Currently this channel is always enabled.
2019-05-09 14:54:25 +00:00
# we have to calculate with an additional dummy channel for TIA
set DMA_DATA_WIDTH [expr $ADC_DATA_WIDTH > 127 ? 256 : \
$ADC_DATA_WIDTH > 63 ? 128 : 64]
ad_fmclidar1_ebz: Initial commit This commit was created by squashing the following commits, these messages were kept just for sake of history: ad9694_500ebz: Mirror the SPI interface to FMCB ad9694_500ebz: Set transceiver reference clock to 250 ad9694_500ebz: Allow to configure number of lanes, number of converters and sample rate axi_ad9694: Fix number of lanes, it must be 2 ad9694_500ebz: Update the mirrored spi pin assignments ad9694_500ebz: Gate SPI MISO signals based on chip-select ad9694_500ebz: Set channel pack sample width ad9694_500ebz: Change reference clock location ad9694_500ebz: Remove transceiver memory map arbitration ad9694_500ebz: Ensure ADC FIFO DMA_DATA_WIDTH is not larger ADC_DATA_WIDTH ad9694_500ebz: Adjust breakout board pin locations ad_fmclidar1_ebz: Rename the ad9694_500ebz project ad_fmclidar1_ebz: Fix lane mapping ad_fmclidar1_ebz: Delete deprecated files ad_fmclidar1_ebz: Integrate the axi_laser_driver into the design ad_fmclidar1_ebz: OTW is an active low signal ad_fmclidar1_ebz: zc706: Fix iic_dac signals assignment ad_fmclidar1_ebz: Switch to util_adcfifo ad_fmclidar1_ebz: Enable synced capture for the fifo ad_fmclidar1_ebz/zc706: Enable CAPTURE_TILL_FULL ad_fmclidar1_ebz/zc706: Reduce FIFO size to 2kB ad_fmclidar1_ebz: Laser driver runs on ADC's core clock ad_fmclidar1_ebz_bd: Delete the FIFO instance Because the DMA transfers are going to be relatively small (< 2kbyte), the DMA can handle the data rate, even when the frequency of the laser driver pulse is set to its maximum value. (200 kHz) The synchronization will be done by connecting the generated pulse to the DMA's SYNC input. Although, to support 2 or 1 channel scenarios, we need to use the util_axis_syncgen module to make sure that the DMA catches the pulse, in cases when the pulse width is too narrow. (SYNC is captures when valid and ready is asserted) Also we have to reset the cpack IP before each pulse, to keep the DMA buffer's relative starting point in time fixed, when only 2 or 1 channel is active.
2017-11-10 13:22:16 +00:00
set SAMPLE_WIDTH [expr $ADC_RESOLUTION > 8 ? 16 : 8]
# add RTL sources which will be instantiated in system_bd directly
adi_project_files ad_fmclidar1_ebz_zc706 [list \
"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
ad_fmclidar1_ebz: Add a dummy ADC channel with TIA channel info Software has to know which TIA channel was used for a particular capture. Define an additional dummy ADC channel which will provide this information. Currently this channel is always enabled.
2019-05-09 14:54:25 +00:00
"../common/util_tia_chsel.v" \
"../common/util_axis_syncgen.v" ]
ad_fmclidar1_ebz: Initial commit This commit was created by squashing the following commits, these messages were kept just for sake of history: ad9694_500ebz: Mirror the SPI interface to FMCB ad9694_500ebz: Set transceiver reference clock to 250 ad9694_500ebz: Allow to configure number of lanes, number of converters and sample rate axi_ad9694: Fix number of lanes, it must be 2 ad9694_500ebz: Update the mirrored spi pin assignments ad9694_500ebz: Gate SPI MISO signals based on chip-select ad9694_500ebz: Set channel pack sample width ad9694_500ebz: Change reference clock location ad9694_500ebz: Remove transceiver memory map arbitration ad9694_500ebz: Ensure ADC FIFO DMA_DATA_WIDTH is not larger ADC_DATA_WIDTH ad9694_500ebz: Adjust breakout board pin locations ad_fmclidar1_ebz: Rename the ad9694_500ebz project ad_fmclidar1_ebz: Fix lane mapping ad_fmclidar1_ebz: Delete deprecated files ad_fmclidar1_ebz: Integrate the axi_laser_driver into the design ad_fmclidar1_ebz: OTW is an active low signal ad_fmclidar1_ebz: zc706: Fix iic_dac signals assignment ad_fmclidar1_ebz: Switch to util_adcfifo ad_fmclidar1_ebz: Enable synced capture for the fifo ad_fmclidar1_ebz/zc706: Enable CAPTURE_TILL_FULL ad_fmclidar1_ebz/zc706: Reduce FIFO size to 2kB ad_fmclidar1_ebz: Laser driver runs on ADC's core clock ad_fmclidar1_ebz_bd: Delete the FIFO instance Because the DMA transfers are going to be relatively small (< 2kbyte), the DMA can handle the data rate, even when the frequency of the laser driver pulse is set to its maximum value. (200 kHz) The synchronization will be done by connecting the generated pulse to the DMA's SYNC input. Although, to support 2 or 1 channel scenarios, we need to use the util_axis_syncgen module to make sure that the DMA catches the pulse, in cases when the pulse width is too narrow. (SYNC is captures when valid and ready is asserted) Also we have to reset the cpack IP before each pulse, to keep the DMA buffer's relative starting point in time fixed, when only 2 or 1 channel is active.
2017-11-10 13:22:16 +00:00
# source all the block designs
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/ad_fmclidar1_ebz_bd.tcl
sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;
2020-10-09 14:28:10 +00:00
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
ad_fmclidar1_ebz: Initial commit This commit was created by squashing the following commits, these messages were kept just for sake of history: ad9694_500ebz: Mirror the SPI interface to FMCB ad9694_500ebz: Set transceiver reference clock to 250 ad9694_500ebz: Allow to configure number of lanes, number of converters and sample rate axi_ad9694: Fix number of lanes, it must be 2 ad9694_500ebz: Update the mirrored spi pin assignments ad9694_500ebz: Gate SPI MISO signals based on chip-select ad9694_500ebz: Set channel pack sample width ad9694_500ebz: Change reference clock location ad9694_500ebz: Remove transceiver memory map arbitration ad9694_500ebz: Ensure ADC FIFO DMA_DATA_WIDTH is not larger ADC_DATA_WIDTH ad9694_500ebz: Adjust breakout board pin locations ad_fmclidar1_ebz: Rename the ad9694_500ebz project ad_fmclidar1_ebz: Fix lane mapping ad_fmclidar1_ebz: Delete deprecated files ad_fmclidar1_ebz: Integrate the axi_laser_driver into the design ad_fmclidar1_ebz: OTW is an active low signal ad_fmclidar1_ebz: zc706: Fix iic_dac signals assignment ad_fmclidar1_ebz: Switch to util_adcfifo ad_fmclidar1_ebz: Enable synced capture for the fifo ad_fmclidar1_ebz/zc706: Enable CAPTURE_TILL_FULL ad_fmclidar1_ebz/zc706: Reduce FIFO size to 2kB ad_fmclidar1_ebz: Laser driver runs on ADC's core clock ad_fmclidar1_ebz_bd: Delete the FIFO instance Because the DMA transfers are going to be relatively small (< 2kbyte), the DMA can handle the data rate, even when the frequency of the laser driver pulse is set to its maximum value. (200 kHz) The synchronization will be done by connecting the generated pulse to the DMA's SYNC input. Although, to support 2 or 1 channel scenarios, we need to use the util_axis_syncgen module to make sure that the DMA catches the pulse, in cases when the pulse width is too narrow. (SYNC is captures when valid and ready is asserted) Also we have to reset the cpack IP before each pulse, to keep the DMA buffer's relative starting point in time fixed, when only 2 or 1 channel is active.
2017-11-10 13:22:16 +00:00
ad_fmclidar1_ebz: Move afe_iic definition to system_bd.tcl In order to prevent platform specific variable usage in the common tcl script, move the AFE I2C interface definition to system_bd.tcl
2019-09-10 14:34:00 +00:00
# I2C for AFE board's DAC
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_dac
ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_IO1_ENABLE 1
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE 1
ad_connect iic_dac sys_ps7/IIC_1
Updated the makefiles to build the projects in subdirectories based on the build parameters. Running 'make' will build the default project directly in the project folder (like it did before) Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory. Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory. Running 'make clean' will clean the default project only. Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build. Running 'make clean-all' will delete all the built configurations and libraries. Note that the 'JESD' and 'LANE' words from the parameter names are stripped. Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-09-23 09:28:22 +00:00
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
ad_fmclidar1_ebz/zc706: Add sys_id support
2019-08-26 15:22:15 +00:00
# System ID instance and configuration
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
Updated the makefiles to build the projects in subdirectories based on the build parameters. Running 'make' will build the default project directly in the project folder (like it did before) Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory. Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory. Running 'make clean' will clean the default project only. Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build. Running 'make clean-all' will delete all the built configurations and libraries. Note that the 'JESD' and 'LANE' words from the parameter names are stripped. Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-09-23 09:28:22 +00:00
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
ad_fmclidar1_ebz/zc706: Add sys_id support
2019-08-26 15:22:15 +00:00
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file
ad_fmclidar1_ebz/zc706: Add sys_id support
2019-08-26 15:22:15 +00:00