2020-03-17 08:15:01 +00:00
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# constraints
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set_property -dict {PACKAGE_PIN BM29 IOSTANDARD LVCMOS12} [get_ports sys_rst]
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# clocks
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# DDR4 Component Memory I/F clock, fixed 100 MHz LVDS [U76]
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set_property -dict {PACKAGE_PIN BH51 IOSTANDARD LVDS} [get_ports sys_clk_p]
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set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD LVDS} [get_ports sys_clk_n]
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# ethernet
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set_property PACKAGE_PIN BG22 [get_ports phy_tx_p]
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set_property PACKAGE_PIN BH22 [get_ports phy_tx_n]
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set_property PACKAGE_PIN BJ22 [get_ports phy_rx_p]
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set_property PACKAGE_PIN BK21 [get_ports phy_rx_n]
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2022-02-14 10:54:42 +00:00
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set_property -dict {PACKAGE_PIN BH27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports phy_clk_p]
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set_property -dict {PACKAGE_PIN BJ27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports phy_clk_n]
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2020-03-17 08:15:01 +00:00
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set_property -dict {PACKAGE_PIN BN27 IOSTANDARD LVCMOS18} [get_ports mdio_mdc]
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set_property -dict {PACKAGE_PIN BG23 IOSTANDARD LVCMOS18} [get_ports mdio_mdio]
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# uart
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set_property -dict {PACKAGE_PIN BP26 IOSTANDARD LVCMOS18} [get_ports uart_sin]
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set_property -dict {PACKAGE_PIN BN26 IOSTANDARD LVCMOS18} [get_ports uart_sout]
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set_property -dict {PACKAGE_PIN BH24 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## GPIO_LED_0_LS
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set_property -dict {PACKAGE_PIN BG24 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## GPIO_LED_1_LS
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set_property -dict {PACKAGE_PIN BG25 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## GPIO_LED_2_LS
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set_property -dict {PACKAGE_PIN BF25 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## GPIO_LED_3_LS
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set_property -dict {PACKAGE_PIN BF26 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## GPIO_LED_4_LS
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set_property -dict {PACKAGE_PIN BF27 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]] ; ## GPIO_LED_5_LS
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set_property -dict {PACKAGE_PIN BG27 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]] ; ## GPIO_LED_6_LS
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set_property -dict {PACKAGE_PIN BG28 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]] ; ## GPIO_LED_7_LS
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# iic
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set_property -dict {PACKAGE_PIN BM27 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_scl]
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set_property -dict {PACKAGE_PIN BL28 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_sda]
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# Create SPI clock
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create_generated_clock -name spi_clk \
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-source [get_pins i_system_wrapper/system_i/axi_spi/ext_spi_clk] \
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-divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi/sck_o]
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# Balance clocks
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#
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# Minimize skew on synchronous CDC timing paths between clocks originating
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# from the same MMCM source. (sys_mem_clk and sys_cpu_clk)
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# This is required mostly by the smart interconnect.
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# Property must be applied directly to the output net of BUFGs.
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set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS \
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[list [get_nets [get_property PARENT [get_nets {i_system_wrapper/system_i/sys_cpu_clk}]]] \
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[get_nets [get_property PARENT [get_nets {i_system_wrapper/system_i/sys_mem_clk}]]] \
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]
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