151 lines
6.4 KiB
VHDL
151 lines
6.4 KiB
VHDL
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---- ----
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---- WISHBONE SPDIF IP Core ----
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---- ----
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---- This file is part of the SPDIF project ----
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---- http://www.opencores.org/cores/spdif_interface/ ----
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---- ----
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---- Description ----
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---- SPDIF receiver status register ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2004/06/27 16:16:55 gedra
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-- Signal renaming and bug fix.
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--
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-- Revision 1.3 2004/06/26 14:14:47 gedra
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-- Converted to numeric_std and fixed a few bugs.
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--
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-- Revision 1.2 2004/06/16 19:03:10 gedra
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-- Added channel status decoding.
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--
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-- Revision 1.1 2004/06/05 17:17:12 gedra
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-- Recevier status register
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--
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity rx_status_reg is
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generic (DATA_WIDTH: integer);
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port (
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up_clk: in std_logic; -- clock
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status_rd: in std_logic; -- status register read
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lock: in std_logic; -- signal lock status
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chas: in std_logic; -- channel A or B select
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rx_block_start: in std_logic; -- start of block signal
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ch_data: in std_logic; -- channel status/user data
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cs_a_en: in std_logic; -- channel status ch. A enable
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cs_b_en: in std_logic; -- channel status ch. B enable
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status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end rx_status_reg;
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architecture rtl of rx_status_reg is
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signal status_vector : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal cur_pos : integer range 0 to 255;
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signal pro_mode : std_logic;
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begin
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status_dout <= status_vector when status_rd = '1' else (others => '0');
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D32: if DATA_WIDTH = 32 generate
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status_vector(31 downto 16) <= (others => '0');
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end generate D32;
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status_vector(0) <= lock;
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status_vector(15 downto 7) <= (others => '0');
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-- extract channel status bits to be used
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CDAT: process (up_clk, lock)
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begin
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if lock = '0' then
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cur_pos <= 0;
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pro_mode <= '0';
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status_vector(6 downto 1) <= (others => '0');
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else
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if rising_edge(up_clk) then
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-- bit counter, 0 to 191
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if rx_block_start = '1' then
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cur_pos <= 0;
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elsif cs_b_en = '1' then -- ch. status #2 comes last, count then
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cur_pos <= cur_pos + 1;
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end if;
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-- extract status bits used in status register
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if (chas = '0' and cs_b_en = '1') or
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(chas = '1' and cs_a_en = '1') then
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case cur_pos is
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when 0 => -- PRO bit
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status_vector(1) <= ch_data;
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pro_mode <= ch_data;
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when 1 => -- AUDIO bit
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status_vector(2) <= not ch_data;
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when 2 => -- emphasis/copy bit
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if pro_mode = '1' then
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status_vector(5) <= ch_data;
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else
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status_vector(6) <= ch_data;
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end if;
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when 3 => -- emphasis
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if pro_mode = '1' then
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status_vector(4) <= ch_data;
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else
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status_vector(5) <= ch_data;
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end if;
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when 4 => -- emphasis
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if pro_mode = '1' then
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status_vector(3) <= ch_data;
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else
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status_vector(4) <= ch_data;
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end if;
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when 5 => -- emphasis
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if pro_mode = '0' then
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status_vector(3) <= ch_data;
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end if;
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when others =>
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null;
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end case;
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end if;
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end if;
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end if;
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end process CDAT;
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end rtl;
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