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pluto_hdl_adi/library/util_axis_upscale/Makefile

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util_axis_upscale: Initial commit This module upscale an n*sample_width data bus into a 16 or 32*n data bus. The samples are right aligned and supports offset binary or two's complement data format.
2017-10-16 09:43:20 +00:00
####################################################################################
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
## Copyright 2018(c) Analog Devices, Inc.
util_axis_upscale: Initial commit This module upscale an n*sample_width data bus into a 16 or 32*n data bus. The samples are right aligned and supports offset binary or two's complement data format.
2017-10-16 09:43:20 +00:00
## Auto-generated, do not modify!
####################################################################################
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
LIBRARY_NAME := util_axis_upscale
util_axis_upscale: Initial commit This module upscale an n*sample_width data bus into a 16 or 32*n data bus. The samples are right aligned and supports offset binary or two's complement data format.
2017-10-16 09:43:20 +00:00
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
GENERIC_DEPS += ../common/util_axis_upscale.v
XILINX_DEPS += util_axis_upscale_ip.tcl
util_axis_upscale: Initial commit This module upscale an n*sample_width data bus into a 16 or 32*n data bus. The samples are right aligned and supports offset binary or two's complement data format.
2017-10-16 09:43:20 +00:00
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
include ../scripts/library.mk