22 lines
785 B
Plaintext
22 lines
785 B
Plaintext
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "4.000 ns" -name rx_device_clk [get_ports {rx_device_clk}]
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create_clock -period "4.000 ns" -name rx_ref_clk [get_ports {rx_ref_clk}]
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# Asynchronous GPIOs
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foreach async_input {adc_fda adc_fdb gpio_bd_i[*]} {
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set_false_path -from [get_ports $async_input]
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}
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foreach async_output {laser_gpio[*] afe_adc_convst afe_dac_load afe_dac_clr_n adc_pdwn gpio_bd_o[*]} {
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set_false_path -to [get_ports $async_output]
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}
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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set_false_path -to [get_registers *i_util_axis_syncgen*i_axis_ext_sync|cdc_sync_stage1*]
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