342 lines
9.5 KiB
Coq
342 lines
9.5 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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i2s_mclk,
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i2s_bclk,
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i2s_lrclk,
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i2s_sdata_out,
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i2s_sdata_in,
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spdif,
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iic_scl,
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iic_sda,
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iic_mux_scl,
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iic_mux_sda,
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otg_vbusoc,
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clk_in,
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ready_in,
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data_in,
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso,
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gpio_0_mode_0,
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gpio_1_mode_1,
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gpio_2_mode_2,
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gpio_3_mode_3,
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gpio_4_filter,
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reset_n,
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start_n,
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sync_n,
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sync_in_n,
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mclk);
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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inout [31:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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output spdif;
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output i2s_mclk;
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output i2s_bclk;
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output i2s_lrclk;
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output i2s_sdata_out;
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input i2s_sdata_in;
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inout iic_scl;
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inout iic_sda;
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inout [ 1:0] iic_mux_scl;
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inout [ 1:0] iic_mux_sda;
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input otg_vbusoc;
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input clk_in;
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input ready_in;
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input [ 7:0] data_in;
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output spi_csn;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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inout gpio_0_mode_0;
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inout gpio_1_mode_1;
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inout gpio_2_mode_2;
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inout gpio_3_mode_3;
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inout gpio_4_filter;
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inout reset_n;
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inout start_n;
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inout sync_n;
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inout sync_in_n;
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output mclk;
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// internal signals
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wire adc_clk;
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wire adc_valid;
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wire [31:0] adc_data;
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wire up_sshot;
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wire [ 1:0] up_format;
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wire up_crc_enable;
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wire up_crc_4_or_16_n;
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wire [63:0] adc_gpio_i;
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wire [63:0] adc_gpio_o;
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wire [63:0] adc_gpio_t;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 1:0] iic_mux_scl_i_s;
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wire [ 1:0] iic_mux_scl_o_s;
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wire iic_mux_scl_t_s;
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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// use crystal
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assign mclk = 1'b0;
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assign up_sshot = gpio_o[36];
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assign up_format = gpio_o[35:34];
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assign up_crc_enable = gpio_o[33];
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assign up_crc_4_or_16_n = gpio_o[32];
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// instantiations
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ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
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.dio_t ({gpio_t[52:48], gpio_t[43:40]}),
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.dio_i ({gpio_o[52:48], gpio_o[43:40]}),
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.dio_o ({gpio_i[52:48], gpio_i[43:40]}),
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.dio_p ({ gpio_4_filter, // 52
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gpio_3_mode_3, // 51
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gpio_2_mode_2, // 50
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gpio_1_mode_1, // 49
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gpio_0_mode_0, // 48
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sync_in_n, // 43
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sync_n, // 42
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start_n, // 41
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reset_n})); // 40
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ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_bd (
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.dio_t (gpio_t[31:0]),
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.dio_i (gpio_o[31:0]),
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.dio_o (gpio_i[31:0]),
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.dio_p (gpio_bd));
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ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_scl (
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.dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}),
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.dio_i (iic_mux_scl_o_s),
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.dio_o (iic_mux_scl_i_s),
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.dio_p (iic_mux_scl));
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ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_sda (
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.dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}),
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.dio_i (iic_mux_sda_o_s),
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.dio_o (iic_mux_sda_i_s),
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.dio_p (iic_mux_sda));
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ad7768_if i_ad7768_if (
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.clk_in (clk_in),
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.ready_in (ready_in),
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.data_in (data_in),
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.adc_clk (adc_clk),
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.adc_valid (adc_valid),
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.adc_data (adc_data),
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.up_sshot (up_sshot),
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.up_format (up_format),
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.up_crc_enable (up_crc_enable),
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.up_crc_4_or_16_n (up_crc_4_or_16_n),
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.up_status_clr (adc_gpio_o[32:0]),
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.up_status (adc_gpio_i[32:0]));
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system_wrapper i_system_wrapper (
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.adc_clk (adc_clk),
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.adc_data (adc_data),
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.adc_gpio_0_i (adc_gpio_i[31:0]),
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.adc_gpio_0_o (adc_gpio_o[31:0]),
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.adc_gpio_0_t (adc_gpio_t[31:0]),
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.adc_gpio_1_i (adc_gpio_i[63:32]),
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.adc_gpio_1_o (adc_gpio_o[63:32]),
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.adc_gpio_1_t (adc_gpio_t[63:32]),
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.adc_valid (adc_valid),
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.i2s_bclk (i2s_bclk),
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.i2s_lrclk (i2s_lrclk),
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.i2s_mclk (i2s_mclk),
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.i2s_sdata_in (i2s_sdata_in),
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.i2s_sdata_out (i2s_sdata_out),
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.iic_fmc_scl_io (iic_scl),
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.iic_fmc_sda_io (iic_sda),
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.iic_mux_scl_i (iic_mux_scl_i_s),
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.iic_mux_scl_o (iic_mux_scl_o_s),
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.iic_mux_scl_t (iic_mux_scl_t_s),
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.iic_mux_sda_i (iic_mux_sda_i_s),
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.iic_mux_sda_o (iic_mux_sda_o_s),
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.iic_mux_sda_t (iic_mux_sda_t_s),
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.otg_vbusoc (otg_vbusoc),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.spdif (spdif),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (spi_clk),
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.spi0_csn_0_o (spi_csn),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (spi_miso),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (spi_mosi),
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.spi1_clk_i (1'b0),
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.spi1_clk_o (),
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.spi1_csn_0_o (),
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.spi1_csn_1_o (),
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.spi1_csn_2_o (),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o ());
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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