zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/projects/cftl_cip/common/cftl_cip_bd.tcl

64 lines
2.2 KiB
Tcl
Raw Normal View History

cftl_cip: Initial check in. Project cftl_cip supports the following Circuits from the Lab pmods: + EVAL-CN0350-PMDZ + EVAL-CN0335-PMDZ + EVAL-CN0336-PMDZ + EVAL-CN0337-PMDZ Note: Additional testing needed!
2015-01-23 16:29:32 +00:00
cftl_cip: Update project to the new frame work.
2015-04-02 12:14:04 +00:00
global adc_spi_freq
# pmod interfaces
create_bd_port -dir O pmod_spi_cs
create_bd_port -dir I pmod_spi_miso
create_bd_port -dir O pmod_spi_clk
create_bd_port -dir O pmod_spi_convst
create_bd_port -dir I pmod_gpio
# instances
set pmod_spi_core [create_bd_cell -type ip -vlnv analog.com:user:util_pmod_adc:1.0 pmod_spi_core]
set_property -dict [list CONFIG.FPGA_CLOCK_MHZ {100}] $pmod_spi_core
set pmod_spi_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 pmod_spi_dma]
cftl_cip/common: Fix parameter names for dmac
2015-09-30 09:32:48 +00:00
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $pmod_spi_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $pmod_spi_dma
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.ID {0}] $pmod_spi_dma
cftl_cip/common: Fix parameter names for dmac
2015-09-30 09:32:48 +00:00
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $pmod_spi_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $pmod_spi_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $pmod_spi_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $pmod_spi_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $pmod_spi_dma
set_property -dict [list CONFIG.CYCLIC {0}] $pmod_spi_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $pmod_spi_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $pmod_spi_dma
cftl_cip: Update project to the new frame work.
2015-04-02 12:14:04 +00:00
set pmod_gpio_core [create_bd_cell -type ip -vlnv analog.com:user:util_pmod_fmeter:1.0 pmod_gpio_core]
# additional configurations
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
ad_connect sys_cpu_clk pmod_spi_dma/fifo_wr_clk
ad_connect sys_cpu_clk pmod_spi_core/clk
ad_connect sys_cpu_clk pmod_gpio_core/ref_clk
util_pmod_adc: Reset line changed to active low reset.
2015-09-30 09:33:46 +00:00
ad_connect pmod_spi_core/resetn sys_rstgen/peripheral_aresetn
cftl_cip: Update project to the new frame work.
2015-04-02 12:14:04 +00:00
ad_connect pmod_spi_core/adc_data pmod_spi_dma/fifo_wr_din
ad_connect pmod_spi_core/adc_valid pmod_spi_dma/fifo_wr_en
ad_connect pmod_spi_miso pmod_spi_core/adc_sdo
ad_connect pmod_spi_clk pmod_spi_core/adc_sclk
ad_connect pmod_spi_cs pmod_spi_core/adc_cs_n
ad_connect pmod_spi_convst pmod_spi_core/adc_convst_n
ad_connect pmod_gpio pmod_gpio_core/square_signal
# interrupts
ad_cpu_interrupt ps-13 mb-12 pmod_spi_dma/irq
# cpu / memory interconnects
ad_cpu_interconnect 0x43010000 pmod_spi_dma
ad_cpu_interconnect 0x43C00000 pmod_gpio_core
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk pmod_spi_dma/m_dest_axi
cftl_cip: Initial check in. Project cftl_cip supports the following Circuits from the Lab pmods: + EVAL-CN0350-PMDZ + EVAL-CN0335-PMDZ + EVAL-CN0336-PMDZ + EVAL-CN0337-PMDZ Note: Additional testing needed!
2015-01-23 16:29:32 +00:00