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pluto_hdl_adi/projects/daq3/common/daq3_bd.tcl

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daq3: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-26 11:34:14 +00:00
#
# Parameter description:
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_S : Number of samples per frame
#
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
daq3: Convert to ADI JESD204 Convert the DAQ3 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 09:26:18 +00:00
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
# TX parameters
daq3: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-26 11:34:14 +00:00
set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
set TX_SAMPLE_WIDTH 16 ; # N/NP
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / \
($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
daq3: update adcfifo/dacfifo
2019-01-22 13:19:47 +00:00
set dac_fifo_name axi_ad9152_fifo
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
# RX parameters
daq3: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-26 11:34:14 +00:00
set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / \
($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
set adc_fifo_name axi_ad9680_fifo
set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
daq3: update adcfifo/dacfifo
2019-01-22 13:19:47 +00:00
daq3: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-26 11:34:14 +00:00
set MAX_TX_NUM_OF_LANES 4
set MAX_RX_NUM_OF_LANES 4
daq3/zc706: Update project with the new transceiver modules
2016-10-05 09:08:11 +00:00
# dac peripherals
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
ad_ip_instance axi_adxcvr axi_ad9152_xcvr
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_ip_parameter axi_ad9152_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
ad_ip_parameter axi_ad9152_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9152_xcvr CONFIG.TX_OR_RX_N 1
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
adi_axi_jesd204_tx_create axi_ad9152_jesd $TX_NUM_OF_LANES
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
adi_tpl_jesd204_tx_create axi_ad9152_tpl_core $TX_NUM_OF_LANES \
$TX_NUM_OF_CONVERTERS \
$TX_SAMPLES_PER_FRAME \
$TX_SAMPLE_WIDTH
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_ip_instance util_upack2 axi_ad9152_upack [list \
NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
]
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
ad_ip_instance axi_dmac axi_ad9152_dma
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_ad9152_dma CONFIG.ID 1
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST 1
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9152_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_SRC 128
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width
daq3: update adcfifo/dacfifo
2019-01-22 13:19:47 +00:00
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# adc peripherals
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
ad_ip_instance axi_adxcvr axi_ad9680_xcvr
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
adi_axi_jesd204_rx_create axi_ad9680_jesd $RX_NUM_OF_LANES
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
adi_tpl_jesd204_rx_create axi_ad9680_tpl_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_ip_instance util_cpack2 axi_ad9680_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
]
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
ad_ip_instance axi_dmac axi_ad9680_dma
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9680_dma CONFIG.ID 0
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0
daq2/fmcadc4/daq3: Disable the transfer start sync on the ADC DMA Explicitly disable the "Transfer Start Synchronisation Support" since the sync lines are not connected in this project. If the sync input line (s_axi_user[0] or fifo_wr_sync) are not connected, Vivado 2017.4.1 no longer connects them to the defaultValue defined in the axi_dmac ip (1). Instead he uses the defaulValue field defined in the interface definition which in case of both interfaces is 0;
2018-02-28 13:37:40 +00:00
ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 0
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_data_width
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
daq3: update adcfifo/dacfifo
2019-01-22 13:19:47 +00:00
if {$sys_zynq == 0 || $sys_zynq == 1} {
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_data_width $adc_fifo_address_width
daq3: update adcfifo/dacfifo
2019-01-22 13:19:47 +00:00
}
daq3/zc706: Update project with the new transceiver modules
2016-10-05 09:08:11 +00:00
# shared transceiver core
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
ad_ip_instance util_adxcvr util_daq3_xcvr
daq3: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-26 11:34:14 +00:00
ad_ip_parameter util_daq3_xcvr CONFIG.RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES
ad_ip_parameter util_daq3_xcvr CONFIG.TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES
daq3: Add parameters for default xcvr configuration The default configuration should be: - line rate 12.33 Gbps - core clk 308 MHz
2018-02-28 08:14:08 +00:00
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV_RATIO 1
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 0x30; # 20
ad_ip_parameter util_daq3_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_daq3_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_daq3_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
ad_ip_parameter util_daq3_xcvr CONFIG.RX_CDR_CFG 0x0B000023FF10400020
daq3/zc706: Update project with the new transceiver modules
2016-10-05 09:08:11 +00:00
block_design: Updates with new reset net variables
2019-05-30 06:43:44 +00:00
ad_connect $sys_cpu_resetn util_daq3_xcvr/up_rstn
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_connect $sys_cpu_clk util_daq3_xcvr/up_clk
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
daq3/zc706- xcvr changes
2016-11-23 20:02:20 +00:00
# reference clocks & resets
create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
ad_xcvrpll tx_ref_clk_0 util_daq3_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_daq3_xcvr/cpll_ref_clk_*
ad_xcvrpll axi_ad9152_xcvr/up_pll_rst util_daq3_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq3_xcvr/up_cpll_rst_*
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# connections (dac)
daq3: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-26 11:34:14 +00:00
ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd {0 2 3 1} {} {} $MAX_TX_NUM_OF_LANES
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_tpl_core/link_clk
ad_connect axi_ad9152_jesd/tx_data axi_ad9152_tpl_core/link
daq3: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-04 10:41:11 +00:00
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/clk
ad_connect axi_ad9152_jesd_rstgen/peripheral_reset axi_ad9152_upack/reset
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_connect axi_ad9152_tpl_core/dac_valid_0 axi_ad9152_upack/fifo_rd_en
for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect axi_ad9152_tpl_core/dac_enable_$i axi_ad9152_upack/enable_$i
ad_connect axi_ad9152_tpl_core/dac_data_$i axi_ad9152_upack/fifo_rd_data_$i
daq3: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-04 10:41:11 +00:00
}
daq3: ZCU102: Remove Offload FIFO for ADC path. DAC FIFO cannot be increased because of timing violations
2018-07-11 07:23:50 +00:00
if {$sys_zynq == 0 || $sys_zynq == 1} {
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_connect $sys_dma_clk axi_ad9152_fifo/dma_clk
ad_connect $sys_dma_reset axi_ad9152_fifo/dma_rst
ad_connect $sys_dma_clk axi_ad9152_dma/m_axis_aclk
ad_connect $sys_dma_resetn axi_ad9152_dma/m_src_axi_aresetn
daq3: ZCU102: Remove Offload FIFO for ADC path. DAC FIFO cannot be increased because of timing violations
2018-07-11 07:23:50 +00:00
ad_connect axi_ad9152_fifo/bypass GND
}
daq3/zc706- xcvr changes
2016-11-23 20:02:20 +00:00
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk
adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection
2017-03-10 12:20:42 +00:00
ad_connect axi_ad9152_jesd_rstgen/peripheral_reset axi_ad9152_fifo/dac_rst
daq3: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-04 10:41:11 +00:00
# TODO: Add streaming AXI interface for DAC FIFO
ad_connect axi_ad9152_upack/s_axis_valid VCC
ad_connect axi_ad9152_upack/s_axis_ready axi_ad9152_fifo/dac_valid
ad_connect axi_ad9152_upack/s_axis_data axi_ad9152_fifo/dac_data
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_connect axi_ad9152_tpl_core/dac_dunf axi_ad9152_fifo/dac_dunf
daq3- bd updates
2015-09-30 14:11:42 +00:00
ad_connect axi_ad9152_fifo/dma_xfer_req axi_ad9152_dma/m_axis_xfer_req
ad_connect axi_ad9152_fifo/dma_ready axi_ad9152_dma/m_axis_ready
ad_connect axi_ad9152_fifo/dma_data axi_ad9152_dma/m_axis_data
ad_connect axi_ad9152_fifo/dma_valid axi_ad9152_dma/m_axis_valid
ad_connect axi_ad9152_fifo/dma_xfer_last axi_ad9152_dma/m_axis_last
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# connections (adc)
daq3: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-26 11:34:14 +00:00
ad_xcvrcon util_daq3_xcvr axi_ad9680_xcvr axi_ad9680_jesd {} {} {} $MAX_RX_NUM_OF_LANES
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_tpl_core/link_clk
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_tpl_core/link_sof
ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_tpl_core/link_data
ad_connect axi_ad9680_jesd/rx_data_tvalid axi_ad9680_tpl_core/link_valid
ad_connect axi_ad9680_tpl_core/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
daq3: ZCU102: Remove Offload FIFO for ADC path. DAC FIFO cannot be increased because of timing violations
2018-07-11 07:23:50 +00:00
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
daq3: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-04 10:41:11 +00:00
ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_connect $sys_dma_clk axi_ad9680_fifo/dma_clk
ad_connect $sys_dma_clk axi_ad9680_dma/s_axis_aclk
ad_connect $sys_dma_resetn axi_ad9680_dma/m_dest_axi_aresetn
daq3: ZCU102: Remove Offload FIFO for ADC path. DAC FIFO cannot be increased because of timing violations
2018-07-11 07:23:50 +00:00
ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_connect axi_ad9680_tpl_core/adc_dovf axi_ad9680_fifo/adc_wovf
daq3: ZCU102: Remove Offload FIFO for ADC path. DAC FIFO cannot be increased because of timing violations
2018-07-11 07:23:50 +00:00
}
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
daq3: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-04 10:41:11 +00:00
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect axi_ad9680_tpl_core/adc_enable_$i axi_ad9680_cpack/enable_$i
ad_connect axi_ad9680_tpl_core/adc_data_$i axi_ad9680_cpack/fifo_wr_data_$i
daq3: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-04 10:41:11 +00:00
}
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interconnect (cpu)
daq3/zc706: Update project with the new transceiver modules
2016-10-05 09:08:11 +00:00
ad_cpu_interconnect 0x44A60000 axi_ad9152_xcvr
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_cpu_interconnect 0x44A04000 axi_ad9152_tpl_core
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_cpu_interconnect 0x44A90000 axi_ad9152_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9152_dma
daq3/zc706: Update project with the new transceiver modules
2016-10-05 09:08:11 +00:00
ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_cpu_interconnect 0x44A10000 axi_ad9680_tpl_core
daq3: Convert to ADI JESD204 Convert the DAQ3 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 09:26:18 +00:00
ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
daq3: ZCU102: Remove Offload FIFO for ADC path. DAC FIFO cannot be increased because of timing violations
2018-07-11 07:23:50 +00:00
if {$sys_zynq == 0 || $sys_zynq == 1} {
daq3: Update projects to the new TPL Also modified the FIFO ports to have the same widths so that in a future commit the bypass would be available for cases when the sampling rate won't be the maximum rate or the number of channels active will be less than maximum number of channels
2020-10-17 14:15:02 +00:00
ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_dma_clk axi_ad9152_dma/m_src_axi
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9680_dma/m_dest_axi
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9680_xcvr/m_axi
daq3: ZCU102: Remove Offload FIFO for ADC path. DAC FIFO cannot be increased because of timing violations
2018-07-11 07:23:50 +00:00
}
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interrupts
Connect JESD204 interrupts Connect the ADI JESD204 link layer peripheral interrupt signals in all projects. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-02 08:24:37 +00:00
ad_cpu_interrupt ps-10 mb-15 axi_ad9152_jesd/irq
ad_cpu_interrupt ps-11 mb-14 axi_ad9680_jesd/irq
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq