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pluto_hdl_adi/projects/ad4134_fmc/Makefile

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projects/ad4134_fmc: Initial commit add support * Updated reference design: spi trigger, ODR parameters - enabled ext_clk for PWM to use 96 MHz spi clk - mofified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK - spi offload trigger signal: PWM trigger used * Moved mem_interconnect to hp1 * Added dclkio GPIO * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-05-06 13:08:39 +00:00
####################################################################################
Check guidelines. Remove redundancies * Removed empty/commented lines * Regenerated Makefiles * Removed redundancies adc channels data width * Set data width 32-bit: max resolution and CRC header Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-23 12:10:43 +00:00
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
projects/ad4134_fmc: Initial commit add support * Updated reference design: spi trigger, ODR parameters - enabled ext_clk for PWM to use 96 MHz spi clk - mofified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK - spi offload trigger signal: PWM trigger used * Moved mem_interconnect to hp1 * Added dclkio GPIO * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-05-06 13:08:39 +00:00
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk