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pluto_hdl_adi/projects/fmcadc2/common/fmcadc2_bd.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
fmcadc2: Parameterize JESD204 configuration values Add the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-07 16:33:27 +00:00
#
# Parameter description:
# RX_JESD_M : Number of converters per link
# RX_JESD_L : Number of lanes per link
# RX_JESD_S : Number of samples per frame
# RX_JESD_NP : Number of bits per sample
#
fmcadc2: Convert to ADI JESD204 Convert the FMCADC2 project to the ADI JESD204 link layer core. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:52:13 +00:00
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
fmcadc2: Update JESD204 TPL instance Updated the JESD204B transport layer instance to instantiate the new TPL IP module. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-03 10:57:27 +00:00
# JESD204B interface configuration parameters
fmcadc2: Parameterize JESD204 configuration values Add the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-07 16:33:27 +00:00
set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L)
set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M)
set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S)
set RX_SAMPLE_WIDTH $ad_project_params(RX_JESD_NP)
fmcadc2: Update JESD204 TPL instance Updated the JESD204B transport layer instance to instantiate the new TPL IP module. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-03 10:57:27 +00:00
fmcadc2: update adcfifo/dacfifo
2019-01-22 13:20:15 +00:00
set adc_fifo_name axi_ad9625_fifo
fmcadc2: Parameterize JESD204 configuration values Add the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-07 16:33:27 +00:00
set adc_data_width [expr 32*$RX_NUM_OF_LANES]
fmcadc2: update adcfifo/dacfifo
2019-01-22 13:20:15 +00:00
set adc_dma_data_width 64
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# adc peripherals
fmcadc2: Update JESD204 TPL instance Updated the JESD204B transport layer instance to instantiate the new TPL IP module. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-03 10:57:27 +00:00
adi_tpl_jesd204_rx_create axi_ad9625_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH \
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
fmcadc2: Parameterize JESD204 configuration values Add the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-07 16:33:27 +00:00
adi_axi_jesd204_rx_create axi_ad9625_jesd $RX_NUM_OF_LANES
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
Ip automatic version update: fmcadc2, fmcadc5
2017-04-12 16:00:33 +00:00
ad_ip_instance axi_adxcvr axi_ad9625_xcvr
fmcadc2: Parameterize JESD204 configuration values Add the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-07 16:33:27 +00:00
ad_ip_parameter axi_ad9625_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
Ip automatic version update: fmcadc2, fmcadc5
2017-04-12 16:00:33 +00:00
ad_ip_parameter axi_ad9625_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9625_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_ad9625_xcvr CONFIG.LPM_OR_DFE_N 1
ad_ip_parameter axi_ad9625_xcvr CONFIG.SYS_CLK_SEL 0
ad_ip_parameter axi_ad9625_xcvr CONFIG.OUT_CLK_SEL 2
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
Ip automatic version update: fmcadc2, fmcadc5
2017-04-12 16:00:33 +00:00
ad_ip_instance axi_dmac axi_ad9625_dma
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9625_dma CONFIG.ID 0
ad_ip_parameter axi_ad9625_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9625_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9625_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9625_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_DEST 64
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
fmcadc2: update adcfifo/dacfifo
2019-01-22 13:20:15 +00:00
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
Ip automatic version update: fmcadc2, fmcadc5
2017-04-12 16:00:33 +00:00
ad_ip_instance util_adxcvr util_fmcadc2_xcvr
util_adxcvr: Fix parameter setup at instantiation If a parameter value is defined as a string binary (e.g. "001001000000"), it can confuse the tool, and the value may be used as a decimal number. To prevent this issue and to improve readability converting all the binary constants into hexadecimal.
2017-04-27 12:35:39 +00:00
ad_ip_parameter util_fmcadc2_xcvr CONFIG.QPLL_FBDIV 0x80 ;# N = 40
Ip automatic version update: fmcadc2, fmcadc5
2017-04-12 16:00:33 +00:00
ad_ip_parameter util_fmcadc2_xcvr CONFIG.CPLL_FBDIV 1
ad_ip_parameter util_fmcadc2_xcvr CONFIG.TX_NUM_OF_LANES 0
fmcadc2: Parameterize JESD204 configuration values Add the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-07 16:33:27 +00:00
ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
Ip automatic version update: fmcadc2, fmcadc5
2017-04-12 16:00:33 +00:00
ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_CLK25_DIV 25
ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_CDR_CFG 0x03000023ff20400020 ;# DFE mode refclk +-200
fmcadc2: xcvr updates
2016-11-21 16:45:38 +00:00
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
# reference clocks & resets
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
create_bd_port -dir I rx_ref_clk_0
fmcadc2: Integrate ad_sysref_gen into the project
2016-12-19 12:16:05 +00:00
create_bd_port -dir O rx_core_clk
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/cpll_ref_clk_*
ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_cpll_rst_*
block_design: Updates with new reset net variables
2019-05-30 06:43:44 +00:00
ad_connect $sys_cpu_resetn util_fmcadc2_xcvr/up_rstn
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_connect $sys_cpu_clk util_fmcadc2_xcvr/up_clk
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# connections (adc)
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
ad_xcvrcon util_fmcadc2_xcvr axi_ad9625_xcvr axi_ad9625_jesd
fmcadc2: Update JESD204 TPL instance Updated the JESD204B transport layer instance to instantiate the new TPL IP module. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-03 10:57:27 +00:00
ad_connect util_fmcadc2_xcvr/rx_out_clk_0 axi_ad9625_core/link_clk
fmcadc2: Fix connection between a db port and a net The block design port should always be the first argument of the ad_connect process call.
2017-08-07 14:00:01 +00:00
ad_connect rx_core_clk util_fmcadc2_xcvr/rx_out_clk_0
fmcadc2: Update JESD204 TPL instance Updated the JESD204B transport layer instance to instantiate the new TPL IP module. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-03 10:57:27 +00:00
ad_connect axi_ad9625_jesd/rx_data_tdata axi_ad9625_core/link_data
ad_connect axi_ad9625_jesd/rx_sof axi_ad9625_core/link_sof
ad_connect axi_ad9625_jesd/rx_data_tvalid axi_ad9625_core/link_valid
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_connect $sys_cpu_clk axi_ad9625_fifo/dma_clk
ad_connect $sys_cpu_clk axi_ad9625_dma/s_axis_aclk
block_design: Updates with new reset net variables
2019-05-30 06:43:44 +00:00
ad_connect $sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
fmcadc2: Update JESD204 TPL instance Updated the JESD204B transport layer instance to instantiate the new TPL IP module. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-03 10:57:27 +00:00
ad_connect axi_ad9625_core/link_clk axi_ad9625_fifo/adc_clk
fmcadc2: Integrate ad_sysref_gen into the project
2016-12-19 12:16:05 +00:00
ad_connect axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
fmcadc2: Update JESD204 TPL instance Updated the JESD204B transport layer instance to instantiate the new TPL IP module. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-03 10:57:27 +00:00
ad_connect axi_ad9625_core/adc_enable_0 axi_ad9625_fifo/adc_wr
ad_connect axi_ad9625_core/adc_data_0 axi_ad9625_fifo/adc_wdata
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interconnect (cpu)
fmcadc2: xcvr updates
2016-11-21 16:45:38 +00:00
ad_cpu_interconnect 0x44A60000 axi_ad9625_xcvr
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_cpu_interconnect 0x44A10000 axi_ad9625_core
fmcadc2: Convert to ADI JESD204 Convert the FMCADC2 project to the ADI JESD204 link layer core. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:52:13 +00:00
ad_cpu_interconnect 0x44AA0000 axi_ad9625_jesd
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
# gt uses hp3, and 100MHz clock for both DRP and AXI4
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9625_xcvr/m_axi
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interconnect (mem/adc)
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9625_dma/m_dest_axi
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interrupts
Connect JESD204 interrupts Connect the ADI JESD204 link layer peripheral interrupt signals in all projects. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-02 08:24:37 +00:00
ad_cpu_interrupt ps-12 mb-13 axi_ad9625_jesd/irq
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_cpu_interrupt ps-13 mb-12 axi_ad9625_dma/irq
fmcadc2: Parameterize JESD204 configuration values Add the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-07 16:33:27 +00:00
# Create dummy outputs for unused Rx lanes
for {set i $RX_NUM_OF_LANES} {$i < 8} {incr i} {
create_bd_port -dir I rx_data_${i}_n
create_bd_port -dir I rx_data_${i}_p
}