pluto_hdl_adi/library/common/altera/ad_cmos_clk.v

// ***************************************************************************
// ***************************************************************************
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`timescale 1ns/100ps

module ad_cmos_clk (

  clk_in,
  clk);

  parameter   DEVICE_TYPE   = 0;
  localparam  SERIES7       = 0;
  localparam  VIRTEX6       = 1;

  input     clk_in;
  output    clk;

  // instantiations

  alt_clk i_clk (
    .rst (1'b0),
    .refclk (clk_in),
    .outclk_0 (clk),
    .locked ());

endmodule

// ***************************************************************************
// ***************************************************************************