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pluto_hdl_adi/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl

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Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact jesd204-licensing@analog.com for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
jesd204_rx/tx: make SYSREF IOB placement optional In case when the SYSREF is connected to an FPGA IO which has a limitation on the IOB register IN_FF clock line and the required ref clock is high we can't use the IOB registers. e.g. the max clock rate on zcu102 HP IO FF is 312MHz but ref clock is 375MHz; If IOB is used in this case a pulse width violation is reported. This change makes the IOB placement selectable in such case or for targets which don't require class 1 operation.
2018-07-23 11:58:46 +00:00
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName [ttcl_add $ComponentName "_constr"] :>
<: setFileExtension ".xdc" :>
<: setFileProcessingOrder late :>
<: set sysref_iob [get_property PARAM_VALUE.SYSREF_IOB] :>
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
<: set async_clk [getBooleanValue "ASYNC_CLK"] :>
<: set link_mode [getBooleanValue "LINK_MODE"] :>
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
set_property ASYNC_REG TRUE \
[get_cells {i_lmfc/sysref_d1_reg}] \
[get_cells {i_lmfc/sysref_d2_reg}]
# Make sure that the device clock to sysref skew is at least somewhat
# predictable
jesd204_rx/tx: make SYSREF IOB placement optional In case when the SYSREF is connected to an FPGA IO which has a limitation on the IOB register IN_FF clock line and the required ref clock is high we can't use the IOB registers. e.g. the max clock rate on zcu102 HP IO FF is 312MHz but ref clock is 375MHz; If IOB is used in this case a pulse width violation is reported. This change makes the IOB placement selectable in such case or for targets which don't require class 1 operation.
2018-07-23 11:58:46 +00:00
set_property IOB <=: $sysref_iob :> \
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
[get_cells {i_lmfc/sysref_r_reg}]
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
<: if {$async_clk} { :>
set link_clk [get_clocks -of_objects [get_ports -quiet {clk}]]
set device_clk [get_clocks -of_objects [get_ports -quiet {device_clk}]]
# sync bits
set_false_path \
-from $link_clk \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
jesd204_rx: Set ASYNC_REG attribute for double syncs
2021-02-24 06:51:17 +00:00
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage2_reg* \
-filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
# sync event i_sync_lmfc
set_false_path -quiet \
-from $device_clk \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
jesd204_rx: Set ASYNC_REG attribute for double syncs
2021-02-24 06:51:17 +00:00
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage2_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
set_false_path -quiet \
-from $link_clk \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
jesd204_rx: Set ASYNC_REG attribute for double syncs
2021-02-24 06:51:17 +00:00
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage2_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
# elastic buffer distributed RAM
set_false_path -quiet \
-from $link_clk \
-to [get_cells -quiet -hier *rd_data_reg* \
-filter {NAME =~ *i_elastic_buffer* && IS_SEQUENTIAL}]
<: if {$link_mode == 2} { :>
# sync bits i_buffer_release_cdc 64b66b
set_false_path \
-from $device_clk \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
jesd204_rx: Set ASYNC_REG attribute for double syncs
2021-02-24 06:51:17 +00:00
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage2_reg* \
-filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
<: } :>
<: } :>