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pluto_hdl_adi/library/axi_dmac/tb/dma_read_tb

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axi_dmac: Add transfer testbenches Add simple transfer testbenches that test the read and write to AXI memory paths of the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-07 12:56:33 +00:00
#!/bin/bash
SOURCE="dma_read_tb.v"
SOURCE+=" axi_read_slave.v axi_slave.v"
axi_dmac: Split transfer handling into separate sub-module Move the transfer logic, including the 2d module, into its own sub-module. This allows testing of the full transfer logic independently of the register map logic. The top-level module now only instantiates the register map and transfer module, but does not have any logic on its own. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-05 05:57:38 +00:00
SOURCE+=" ../axi_dmac_transfer.v ../2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
axi_dmac: Rework data store-and-forward buffer Currently the DMAC uses a simple FIFO as the store-and-forward buffer. The FIFO handshaking is beat based whereas the remainder of the DMAC is burst based. This means that additional control signals have to be combined with the FIFO handshaking signal to generate the external handshaking signals. Re-work the store-and-forward buffer to utilize a BRAM that is subdivided into N segments. Where N is the maximum number of bursts that can be stored in the buffer and each segment has the size of the maximum burst length. Each segment stores the data associated with one burst and even when the burst is shorter than the maximum burst length the next burst will be stored in the next segment. The new store-and-forward buffer takes care of generating all the handshaking signals. This means handshaking is generated in a central place and does not have to be combined from multiple data-paths simplifying the overall logic. The new store-and-forward buffer also takes care of data width up- and down-sizing in case that the source and sink modules have a different data width. This tighter integration will allow future enhancements like using asymmetric memory. This re-work lays the foundation of future enhancements to the DMA like support for un-aligned transfers and early transfer abort which would have been much more difficult to implement with the previous architecture. In addition it significantly reduces the resource utilization of the store-and-forward buffer and allows for better timing due to reduced combinatorial path lengths. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-09 16:02:41 +00:00
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
axi_dmac: Eliminate beat counter for the destination interfaces Currently both the source side and the destination side interfaces employ a beat counter to identify the last beat in a burst. The burst memory already has an internal last signal on the destination side. Exporting it allows the destination side interfaces to use it instead of having to generate their own signal. This allows to eliminate the beat counters on the destination side and simplify the data path logic. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-22 12:40:08 +00:00
SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"
axi_dmac: Add transfer testbenches Add simple transfer testbenches that test the read and write to AXI memory paths of the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-07 12:56:33 +00:00
SOURCE+=" ../dest_fifo_inf.v"
axi_dmac: component level testbench updates
2018-08-30 19:34:53 +00:00
SOURCE+=" ../axi_dmac_response_manager.v"
axi_dmac: Add transfer testbenches Add simple transfer testbenches that test the read and write to AXI memory paths of the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-07 12:56:33 +00:00
SOURCE+=" ../src_axi_mm.v ../address_generator.v ../response_generator.v"
axi_dmac: Rework data store-and-forward buffer Currently the DMAC uses a simple FIFO as the store-and-forward buffer. The FIFO handshaking is beat based whereas the remainder of the DMAC is burst based. This means that additional control signals have to be combined with the FIFO handshaking signal to generate the external handshaking signals. Re-work the store-and-forward buffer to utilize a BRAM that is subdivided into N segments. Where N is the maximum number of bursts that can be stored in the buffer and each segment has the size of the maximum burst length. Each segment stores the data associated with one burst and even when the burst is shorter than the maximum burst length the next burst will be stored in the next segment. The new store-and-forward buffer takes care of generating all the handshaking signals. This means handshaking is generated in a central place and does not have to be combined from multiple data-paths simplifying the overall logic. The new store-and-forward buffer also takes care of data width up- and down-sizing in case that the source and sink modules have a different data width. This tighter integration will allow future enhancements like using asymmetric memory. This re-work lays the foundation of future enhancements to the DMA like support for un-aligned transfers and early transfer abort which would have been much more difficult to implement with the previous architecture. In addition it significantly reduces the resource utilization of the store-and-forward buffer and allows for better timing due to reduced combinatorial path lengths. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-09 16:02:41 +00:00
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
SOURCE+=" ../../util_cdc/sync_bits.v"
axi_dmac: component level testbench updates
2018-08-30 19:34:53 +00:00
SOURCE+=" ../../util_cdc/sync_event.v"
axi_dmac: burst_memory: Add support for using asymmetric memory FPGAs support different widths for the read and write port of the block SRAM cells. The DMAC can make use of this feature when the source and destination interface have a different width to up-size/down-size the data bus. Using memory cells with asymmetric port width consumes the same amount of SRAM cells, but allows to bypass the re-size blocks inside the DMAC that are otherwise used for up- and down-sizing. This reduces overall resource usage and can improve timing. If the ratio between the destination and source port is too larger to be handled by SRAM alone the SRAM block will be configured to do partial up- or down-sizing and a resize block will be inserted to take care of the remaining up-/down-sizing. E.g. if a 256-bit interface is connected to a 32-bit interface the SRAM will be used to do an initial resizing of 256 bit to 64 bit and a resize block will be used to do the remaining resizing from 64 bit to 32 bit. Currently this feature is disabled for Intel FPGAs since Quartus does not properly infer a block RAM with different read and write port widths from the current ad_asym_mem module. Once that has been resolved support for asymmetric memories can also be enabled in the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-08 09:43:43 +00:00
SOURCE+=" ../../common/ad_mem_asym.v"
axi_dmac: Add transfer testbenches Add simple transfer testbenches that test the read and write to AXI memory paths of the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-07 12:56:33 +00:00
cd `dirname $0`
source run_tb.sh