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cn0577: Initial commit Created a virtual clock to constrain cnv_en. Given that the cnv_en should be asserted only once per 8 clock cycles and only the rise edge is of interest, we can constrain the path as multicycle path.
2022-02-07 08:22:46 +00:00
# CN0577 HDL Project
Here are some pointers to help you:
projects: Update readmes all projects initial version Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-07-21 09:40:49 +00:00
* [Board Product Page](https://www.analog.com/CN0577)
cn0577: Initial commit Created a virtual clock to constrain cnv_en. Given that the cnv_en should be asserted only once per 8 clock cycles and only the rise edge is of interest, we can constrain the path as multicycle path.
2022-02-07 08:22:46 +00:00
* Parts: [SAR ADC, LVDS interface, 18-bit resolution, Sample rate up to 15MSPS](https://www.analog.com/ltc2387-18)
* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577/hdl
* Project Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577
projects: Update readmes all projects initial version Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-07-21 09:40:49 +00:00
* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ltc2387
cn0577: Initial commit Created a virtual clock to constrain cnv_en. Given that the cnv_en should be asserted only once per 8 clock cycles and only the rise edge is of interest, we can constrain the path as multicycle path.
2022-02-07 08:22:46 +00:00