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pluto_hdl_adi/library/jesd204/jesd204_rx/jesd204_rx_constr.sdc

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Add copyright & license for all files needing ADI JESD specific license * Added every year when the file was edited, with comma * Range if it's consecutive years Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-08-18 07:55:04 +00:00
###############################################################################
## Copyright (C) 2017, 2020, 2021 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
jesd204: Add Altera/Intel IP support Add Qsys IP scripts as well as SDC constraint files for the ADI JESD204 peripherals. This allows them to be instantiated and used on Altera/Intel platforms. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 03:59:33 +00:00
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
set script_dir [file dirname [info script]]
source "$script_dir/util_cdc_constr.tcl"
jesd204: Add Altera/Intel IP support Add Qsys IP scripts as well as SDC constraint files for the ADI JESD204 peripherals. This allows them to be instantiated and used on Altera/Intel platforms. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 03:59:33 +00:00
# SYNC~ is a asynchronous interface
set_false_path \
jesd204_rx: Fix SDC constraint
2019-08-28 05:37:35 +00:00
-from [get_registers *|jesd204_rx_ctrl:i_rx_ctrl|sync_n[0]]
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
util_cdc_sync_bits_constr {*|sync_bits:i_all_buffer_ready_cdc}
util_cdc_sync_event_constr {*|sync_event:i_sync_lmfc}