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pluto_hdl_adi/library/axi_dmac/axi_dmac_constr.xdc

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axi_dmac: Fixed constraints for axi_dmac core
2014-10-22 10:07:55 +00:00
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]]
set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]]
# if ... else does not work in xdc files, but expr, well ok...
set async_src_to_req_clk [expr {$req_clk != $src_clk ? $src_clk : {}}]
set async_req_to_src_clk [expr {$req_clk != $src_clk ? $req_clk : {}}]
set async_dest_to_req_clk [expr {$req_clk != $dest_clk ? $dest_clk : {}}]
set async_req_to_dest_clk [expr {$req_clk != $dest_clk ? $req_clk : {}}]
set async_dest_to_src_clk [expr {$src_clk != $dest_clk ? $dest_clk : {}}]
set async_src_to_dest_clk [expr {$src_clk != $dest_clk ? $src_clk : {}}]
axi_dmac: Fixed constraints for axi_dmac core
2014-10-22 10:07:55 +00:00
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
set_property ASYNC_REG TRUE \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
[get_cells -quiet -hier *cdc_sync_stage1_reg*] \
[get_cells -quiet -hier *cdc_sync_stage2_reg*]
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
#proc get_flops {name inst} {
# return [get_cells -hier $name \
# -filter [format {NAME =~ *%s* && PRIMITIVE_SUBGROUP == flop} $name]]
#}
#
#proc set_single_bit_cdc_constraints {name clk} {
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
# set_false_path -from $clk -to [get_flops *cdc_sync_stage1_reg* ${name}]
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
#}
#
#proc set_multi_bit_cdc_constraints {name clk} {
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
# set_max_delay -from $clk -to [get_flops *cdc_sync_stage1_reg* ${name}] \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
# [get_property PERIOD $clk] -datapath_only
#}
#
#proc set_fifo_cdc_constraints {name clk_a clk_b} {
# set_multi_bit_cdc_constraints ${name}/i_waddr_sync $clk_a
# set_multi_bit_cdc_constraints ${name}/i_raddr_sync $clk_b
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
# set_max_delay -from [get_flops *cdc_sync_fifo_ram_reg* ${name}] -to $clk_b [get_property PERIOD $clk_b] -datapath_only
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
#}
#set_multi_bit_constraints i_sync_src_request_id $req_clk
#set_multi_bit_constraints i_sync_dest_request_id $src_clk
#set_multi_bit_constraints i_sync_req_response_id $dest_clk
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_req_to_src_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_sync_src_request_id* && PRIMITIVE_SUBGROUP == flop}] \
[get_property PERIOD $req_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_src_to_dest_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_sync_dest_request_id* && PRIMITIVE_SUBGROUP == flop}] \
[get_property PERIOD $src_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_dest_to_req_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_sync_req_response_id* && PRIMITIVE_SUBGROUP == flop}] \
[get_property PERIOD $dest_clk] -datapath_only
#set_single_bit_cdc_constraints i_sync_status_src $src_clk
#set_single_bit_cdc_constraints i_sync_control_src $req_clk
#set_single_bit_cdc_constraints i_sync_status_dest $dest_clk
#set_single_bit_cdc_constraints i_sync_control_dest $req_clk
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_false_path -quiet \
-from $async_src_to_req_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_sync_status_src* && PRIMITIVE_SUBGROUP == flop}]
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_false_path -quiet \
-from $async_req_to_src_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_sync_control_src* && PRIMITIVE_SUBGROUP == flop}]
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_false_path -quiet \
-from $async_dest_to_req_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_sync_status_dest* && PRIMITIVE_SUBGROUP == flop}]
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_false_path -quiet \
-from $async_req_to_dest_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_sync_control_dest* && PRIMITIVE_SUBGROUP == flop}]
#set_fifo_cdc_constraints i_dest_req_fifo $req_clk $dest_clk
#set_fifo_cdc_constraints i_dest_response_fifo $dest_clk $req_clk
#set_fifo_cdc_constraints i_src_req_fifo $req_clk $src_clk
#set_fifo_cdc_constraints i_src_response_fifo $src_clk $req_clk
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_req_to_dest_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
[get_property PERIOD $req_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_dest_to_req_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
[get_property PERIOD $dest_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_dest_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
-to $async_dest_to_req_clk \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
[get_property PERIOD $dest_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_dest_to_req_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
[get_property PERIOD $dest_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_req_to_dest_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
[get_property PERIOD $req_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_dest_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
-to $async_req_to_dest_clk \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
[get_property PERIOD $req_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_req_to_src_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
[get_property PERIOD $req_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_src_to_req_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
[get_property PERIOD $src_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_src_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
-to $async_src_to_req_clk \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
[get_property PERIOD $src_clk] -datapath_only
#set_max_delay \
# -from $src_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
# -to [get_cells -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
# -filter {NAME =~ *i_src_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
# [get_property PERIOD $src_clk] -datapath_only
#set_max_delay \
# -from $req_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
# -to [get_cells -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
# -filter {NAME =~ *i_src_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
# [get_property PERIOD $req_clk] -datapath_only
#set_max_delay \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
# -from [get_cells -hier *cdc_sync_fifo_ram_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
# -filter {NAME =~ *i_src_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \
# -to $req_clk \
# [get_property PERIOD $req_clk] -datapath_only
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
#set_max_delay -from [get_flops *eot_mem_reg* i_request_arb] -to $src_clk [get_property PERIOD $src_clk] -datapath_only
#set_max_delay -from [get_flops *eot_mem_reg* i_request_arb] -to $dest_clk [get_property PERIOD $dest_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-from [get_cells -quiet -hier *eot_mem_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
-to $async_src_to_req_clk [get_property PERIOD $src_clk] -datapath_only
set_max_delay -quiet \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-from [get_cells -quiet -hier *eot_mem_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
-to $async_dest_to_req_clk [get_property PERIOD $dest_clk] -datapath_only
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
#set_fifo_cdc_constraints i_fifo $src_clk $dest_clk
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_src_to_dest_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
[get_property PERIOD $src_clk] -datapath_only
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_dest_to_src_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
[get_property PERIOD $dest_clk] -datapath_only
# Reset signals
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_false_path -quiet \
ad9361: axi_dmac_constr: Fix typo
2015-04-16 07:56:54 +00:00
-from $req_clk \
axi_dmac: Make internal resets active high All the FPGA internal control signals are active high, using a active low reset inserts a extra invert LUT. By using a active high reset we can avoid that. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:00:13 +00:00
-to [get_pins -quiet -hier *reset_shift_reg*/PRE]
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
# Not sure why, but it seems the built-in constraints for the RAM36B are wrong
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_max_delay -quiet \
-from $async_dest_to_src_clk \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_pins -hier *ram_reg*/REGCEB -filter {NAME =~ *i_fifo*}] \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
[get_property PERIOD $dest_clk] -datapath_only
# Ignore timing for debug signals to register map
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_false_path -quiet \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {name =~ *i_sync_src_request_id* && primitive_subgroup == flop}] \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_false_path -quiet \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
axi_dmac: Set proper constraints Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-14 17:53:36 +00:00
-filter {name =~ *i_sync_dest_request_id* && primitive_subgroup == flop}] \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
axi_dmac: Only apply CDC constraints if clocks are asynchronous We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 15:14:39 +00:00
set_false_path -quiet \
-from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && primitive_subgroup == flop}] \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
axi_dmac: Ignore timing on more debug signals Ignore the timing path from the current DMA address to the register map, this is just a debug signal at the moment. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-21 16:41:24 +00:00
set_false_path -quiet \
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 13:34:06 +00:00
-from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && primitive_subgroup == flop}] \
-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]