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pluto_hdl_adi/projects/daq2/vc707/system_bd.tcl

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daq2: Initial check in of the VC707 based project NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
2015-01-28 14:24:06 +00:00
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
daq2: Initial check in of the VC707 based project NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
2015-01-28 14:24:06 +00:00
source ../common/daq2_bd.tcl
daq2/vc707: 2014.4 updates
2015-03-26 18:02:31 +00:00