294 lines
9.1 KiB
Tcl
294 lines
9.1 KiB
Tcl
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## ***************************************************************************
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## ***************************************************************************
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## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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##
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## In this HDL repository, there are many different and unique modules, consisting
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## of various HDL (Verilog or VHDL) components. The individual modules are
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## developed independently, and may be accompanied by separate and unique license
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## terms.
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##
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## The user should read each of these license terms, and understand the
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## freedoms and responsibilities that he or she has by using this source/core.
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##
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## This core is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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## A PARTICULAR PURPOSE.
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##
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## Redistribution and use of source or resulting binaries, with or without modification
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## of this file, are permitted under one of the following two license terms:
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##
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## 1. The GNU General Public License version 2 as published by the
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## Free Software Foundation, which can be found in the top level directory
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## of this repository (LICENSE_GPL2), and also online at:
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## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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##
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## OR
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##
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## 2. An ADI specific BSD license, which can be found in the top level directory
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## of this repository (LICENSE_ADIBSD), and also on-line at:
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## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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## This will allow to generate bit files and not release the source code,
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## as long as it attaches to an ADI device.
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##
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## ***************************************************************************
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## ***************************************************************************
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##############################################################################
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## The folowing procedures are available:
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##
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## adi_make::lib <args>
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## -"all"(project libraries)
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## -"library name to build (plus path to it relative to library folder)
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## e.g.: adi_make_lib xilinx/util_adxcvr
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## adi_make::boot_bin - expected that u-boot*.elf (plus bl31.elf for zynq_mp)
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## files are in the project folder"
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## For more info please see: https://wiki.analog.com/resources/fpga/docs/build
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namespace eval adi_make {
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##############################################################################
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# to print debug step messages "set debug_msg=1" (set adi_make::debug_msg 1)
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variable debug_msg 0
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##############################################################################
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variable library_dir
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variable PWD [pwd]
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variable root_hdl_folder
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variable done_list ""
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variable indent_level ""
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# get library absolute path
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set root_hdl_folder ""
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set glb_path $PWD
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if { [regexp projects $glb_path] } {
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regsub {/projects.*$} $glb_path "" root_hdl_folder
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} else {
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puts "ERROR: Not in hdl/* folder"
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return
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}
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set library_dir "$root_hdl_folder/library"
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#----------------------------------------------------------------------------
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# have debug messages
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proc puts_msg { message } {
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variable debug_msg
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variable indent_level
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if { $debug_msg == 1 } {
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puts $indent_level$message
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}
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}
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#----------------------------------------------------------------------------
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# returns the projects required set of libraries
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proc get_libraries {} {
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set build_list ""
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set search_pattern "LIB_DEPS.*="
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set fp1 [open ./Makefile r]
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set file_data [read $fp1]
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close $fp1
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set lines [split $file_data \n]
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foreach line $lines {
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if { [regexp $search_pattern $line] } {
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regsub -all $search_pattern $line "" library
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set library [string trim $library]
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puts_msg "\t- project dep: $library"
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append build_list "$library "
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}
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}
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return $build_list
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}
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#----------------------------------------------------------------------------
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proc lib { libraries } {
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variable library_dir
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variable PWD
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variable done_list
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set build_list $libraries
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if { $libraries == "all" } {
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set build_list "[get_libraries]"
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}
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set libraries ""
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puts "Building:"
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foreach b_lib $build_list {
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puts "- $b_lib"
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append libraries "$library_dir/$b_lib "
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}
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puts "Please wait, this might take a few minutes"
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# searching for subdir libraries in path of the given args
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set first_lib [lindex $libraries 0]
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if { $first_lib == "" } {
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set first_lib "."
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}
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# getting all (libraries)
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set index 0
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set library_element(1) $first_lib
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foreach argument $libraries {
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incr index 1
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set library_element($index) $argument
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}
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# search for all possible IPs in the given argument paths
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set makefiles ""
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if { $index == 0 } {
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set index 1
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}
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for {set y 1} {$y<=$index} {incr y} {
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set dir "$library_element($y)/"
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#search 4 level subdirectories for Makefiles
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for {set x 1} {$x<=4} {incr x} {
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catch { append makefiles " [glob "${dir}Makefile"]" } err
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append dir "*/"
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}
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}
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if { $makefiles == "" } {
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puts "ERROR: Wrong path to IP or the IP does not have a Makefile starting from \"$library_element(1)\""
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}
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# filter out non buildable libs (non *_ip.tcl)
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set buildable ""
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foreach fs $makefiles {
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set lib_dir [file dirname $fs]
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set lib_name "[file tail $lib_dir]_ip.tcl"
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if { [file exists $lib_dir/$lib_name] } {
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append buildable "$fs "
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}
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}
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set makefiles $buildable
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# build all detected IPs
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foreach fs $makefiles {
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regsub /Makefile $fs "" fs
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if { $fs == "." } {
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set fs [string trim [file tail [file normalize $fs]]]
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}
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regsub .*library/ $fs "" fs
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build_lib $fs
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}
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cd $PWD
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set done_list ""
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}
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#----------------------------------------------------------------------------
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# IP build procedure
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proc build_lib { library } {
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variable done_list
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variable library_dir
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variable indent_level
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append indent_level "\t" ;# debug messages
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puts_msg "DEBUG build_lib proc (recursive called)"
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# determine if the IP was previously built in the current adi_make_lib.tcl call
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if { [regexp $library $done_list] } {
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puts_msg "> Build previously done on $library"
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regsub . $indent_level "" indent_level
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return
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} else {
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puts_msg "- Start build of $library"
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}
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puts_msg "- Search dependencies for $library"
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# search for current IP dependencies
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# define library dependency search (Makefiles)
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set serch_pattern "XILINX_.*_DEPS.*="
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set dep_list ""
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set fp1 [open $library_dir/$library/Makefile r]
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set file_data [read $fp1]
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close $fp1
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set lines [split $file_data \n]
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foreach line $lines {
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if { [regexp $serch_pattern $line] } {
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regsub -all $serch_pattern $line "" lib_dep
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set lib_dep [string trim $lib_dep]
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puts_msg "\t$library is dependent on $lib_dep"
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append dep_list "$lib_dep "
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}
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}
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foreach lib $dep_list {
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build_lib $lib
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}
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puts_msg "- Continue build on $library"
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set lib_name "[file tail $library]_ip"
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cd $library_dir/${library}
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exec vivado -mode batch -source "$library_dir/${library}/${lib_name}.tcl"
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file copy -force ./vivado.log ./${lib_name}.log
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puts "- Done building $library"
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append done_list $library
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regsub . $indent_level "" indent_level
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}
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#----------------------------------------------------------------------------
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# boot_bin build procedure
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proc boot_bin {} {
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variable root_hdl_folder
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set arm_tr_sw_elf "bl31.elf"
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set boot_bin_folder "boot_bin"
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if {[catch {set hdf_file "[glob "./*.sdk/system_top.hdf"]"} fid]} {
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puts stderr "ERROR: $fid\n\rNOTE: you must have built hdl project\n\
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\rSee: https://wiki.analog.com/resources/fpga/docs/build\n"
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return
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}
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if {[catch {set uboot_elf "[glob "./u-boot*.elf"]" } fid]} {
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puts stderr "ERROR: $fid\n\rNOTE: you must have a the u-boot.elf in [pwd]\n\
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\rSee: https://wiki.analog.com/resources/fpga/docs/build\n"
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return
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}
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puts "root_hdl_folder $root_hdl_folder"
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puts "uboot_elf $uboot_elf"
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puts "hdf_file $hdf_file"
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# determine if Xilinx SDK tools are set in the enviroment
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package require platform
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set os_type [platform::generic]
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if { [regexp ^win $os_type] } {
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set w_cmd where
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} elseif { [regexp ^linux $os_type] } {
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set w_cmd which
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} else {
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puts "ERROR: Unknown OS: $os_type"
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exit 1
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}
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set xsct_loc [exec $w_cmd xsct]
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# search for Xilinx Command Line Tool (SDK)
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if { $xsct_loc == "" } {
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puts $env(PATH)
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puts "ERROR: SDK not installed or it is not defined in the enviroment path"
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exit 1
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}
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set xsct_script "exec xsct $root_hdl_folder/projects/scripts/adi_make_boot_bin.tcl"
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set build_args "$hdf_file $uboot_elf $boot_bin_folder $arm_tr_sw_elf"
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puts "Please wait, this may take a few minutes."
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eval $xsct_script $build_args
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}
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} ;# ad_make namespace
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#############################################################################
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#############################################################################
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