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pluto_hdl_adi/projects/ad7134_fmc/common/ad7134_bd.tcl

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Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad713x_di
ad7134_fmc: Change ODR signal to output FPGA is now generating the ODR signal using axi_pwm_gen. Both ADCs are now in slave mode.
2021-07-06 11:16:31 +00:00
create_bd_port -dir O ad713x_odr
Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
create_bd_port -dir O ad713x_sdpclk
# create a SPI Engine architecture for the parallel data interface of AD713x
# this design supports AD7132/AD7134/AD7136
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR * Updated bd spi hierarchy, see library/spi_engine.tcl * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-01 18:43:11 +00:00
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
Check guidelines. Remove redundancies * Removed empty/commented lines * Regenerated Makefiles * Removed redundancies adc channels data width * Set data width 32-bit: max resolution and CRC header Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-23 12:10:43 +00:00
set data_width 32
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR * Updated bd spi hierarchy, see library/spi_engine.tcl * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-01 18:43:11 +00:00
set async_spi_clk 1
set num_cs 1
Check guidelines. Remove redundancies * Removed empty/commented lines * Regenerated Makefiles * Removed redundancies adc channels data width * Set data width 32-bit: max resolution and CRC header Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-23 12:10:43 +00:00
set num_sdi 8
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR * Updated bd spi hierarchy, see library/spi_engine.tcl * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-01 18:43:11 +00:00
set num_sdo 0
set sdi_delay 0
set echo_sclk 0
set hier_spi_engine dual_ad7134
spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
ad7134_fmc: Switch offload trigger to falling ODR
2022-01-11 21:31:38 +00:00
# clkgen
ad_ip_instance axi_clkgen axi_ad7134_clkgen
ad_ip_parameter axi_ad7134_clkgen CONFIG.VCO_DIV 5
ad_ip_parameter axi_ad7134_clkgen CONFIG.VCO_MUL 48
ad_ip_parameter axi_ad7134_clkgen CONFIG.CLK0_DIV 10
Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
# dma to receive data stream
ad_ip_instance axi_dmac axi_ad7134_dma
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad7134_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad7134_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_2D_TRANSFER 0
Check guidelines. Remove redundancies * Removed empty/commented lines * Regenerated Makefiles * Removed redundancies adc channels data width * Set data width 32-bit: max resolution and CRC header Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-23 12:10:43 +00:00
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_SRC 256
Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad7134_fmc: Change ODR signal to output FPGA is now generating the ODR signal using axi_pwm_gen. Both ADCs are now in slave mode.
2021-07-06 11:16:31 +00:00
# odr generator
ad_ip_instance axi_pwm_gen odr_generator
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR * Updated bd spi hierarchy, see library/spi_engine.tcl * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-01 18:43:11 +00:00
ad_ip_parameter odr_generator CONFIG.N_PWMS 2
ad_ip_parameter odr_generator CONFIG.PULSE_0_PERIOD 85
ad_ip_parameter odr_generator CONFIG.PULSE_0_WIDTH 1
ad_ip_parameter odr_generator CONFIG.PULSE_0_OFFSET 3
ad_ip_parameter odr_generator CONFIG.PULSE_1_PERIOD 85
ad_ip_parameter odr_generator CONFIG.PULSE_1_WIDTH 13
ad7134_fmc: Switch offload trigger to falling ODR
2022-01-11 21:31:38 +00:00
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR * Updated bd spi hierarchy, see library/spi_engine.tcl * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-01 18:43:11 +00:00
ad_connect odr_generator/ext_clk axi_ad7134_clkgen/clk_0
ad_connect odr_generator/pwm_0 $hier_spi_engine/trigger
ad_connect odr_generator/pwm_1 ad713x_odr
ad7134_fmc: Change ODR signal to output FPGA is now generating the ODR signal using axi_pwm_gen. Both ADCs are now in slave mode.
2021-07-06 11:16:31 +00:00
Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
# sdpclk clock generator - default clk0_out is 50 MHz
ad_ip_instance axi_clkgen axi_sdp_clkgen
ad_ip_parameter axi_sdp_clkgen CONFIG.CLKIN_PERIOD 10
ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_MUL 12
ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_DIV 2
ad_ip_parameter axi_sdp_clkgen CONFIG.CLK0_DIV 12
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR * Updated bd spi hierarchy, see library/spi_engine.tcl * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-01 18:43:11 +00:00
ad_connect axi_ad7134_clkgen/clk_0 $hier_spi_engine/spi_clk
ad_connect $sys_cpu_clk axi_ad7134_clkgen/clk
ad_connect $sys_cpu_clk $hier_spi_engine/clk
ad7134_fmc: Switch offload trigger to falling ODR
2022-01-11 21:31:38 +00:00
ad_connect axi_ad7134_clkgen/clk_0 axi_ad7134_dma/s_axis_aclk
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR * Updated bd spi hierarchy, see library/spi_engine.tcl * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-01 18:43:11 +00:00
ad_connect $sys_cpu_clk axi_sdp_clkgen/clk
ad_connect sys_cpu_resetn $hier_spi_engine/resetn
Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
ad_connect sys_cpu_resetn axi_ad7134_dma/m_dest_axi_aresetn
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR * Updated bd spi hierarchy, see library/spi_engine.tcl * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-01 18:43:11 +00:00
ad_connect $hier_spi_engine/m_spi ad713x_di
ad_connect axi_ad7134_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
ad_connect ad713x_sdpclk axi_sdp_clkgen/clk_0
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR * Updated bd spi hierarchy, see library/spi_engine.tcl * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-01 18:43:11 +00:00
# AXI address definitions
ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
ad_cpu_interconnect 0x44a30000 axi_ad7134_dma
ad_cpu_interconnect 0x44a40000 axi_sdp_clkgen
ad7134_fmc: Change ODR signal to output FPGA is now generating the ODR signal using axi_pwm_gen. Both ADCs are now in slave mode.
2021-07-06 11:16:31 +00:00
ad_cpu_interconnect 0x44b00000 odr_generator
ad7134_fmc: Switch offload trigger to falling ODR
2022-01-11 21:31:38 +00:00
ad_cpu_interconnect 0x44b10000 axi_ad7134_clkgen
Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR * Updated bd spi hierarchy, see library/spi_engine.tcl * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-01 18:43:11 +00:00
# interrupts
Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
ad_cpu_interrupt "ps-13" "mb-13" axi_ad7134_dma/irq
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR * Updated bd spi hierarchy, see library/spi_engine.tcl * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-01 18:43:11 +00:00
ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
# memory interconnects
Revert "Move GTM projects to gtm_projects branch" This reverts commit 171093eca4916defb879a6a9190d8b49f6af0184.
2019-03-21 06:24:45 +00:00
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad7134_dma/m_dest_axi